Round-up 2012: Best of electronics, semiconductors and solar

Friends, here is the round-up of 2012, where the best of electronics, semiconductors and solar PV are presented. Best wishes for a very happy and prosperous new year!

A word on the horrendous Delhi rape that has shaken up India. I am very ashamed to be a man and a part of India's society. My family and I are extremely sorry that the brave girl is no more! May her soul rest in peace. May God deliver justice, and quickly!

DECEMBER 2012
Opportunities in turbulent PV equipment market

Global semiconductor industry outlook 2013: Jaswinder Ahuja, Cadence

Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

Global medical image sensors market to grow 64 percent by 2017

Status of power semiconductor devices industry

NOVEMBER 2012
Global solar PV industry to remain under pressure in 2013!

Dr. Wally Rhines on global semiconductor industry outlook 2013

Focus on monolithic 3D-ICs paradigm shift for semicon industry

Xilinx announces 20nm portfolio strategy

Elliptic intros world’s first commercial touchless gesturing technology!

Global semiconductor industry outlook 2013: Analog Devices

IMEC’s 450mm R&D initiative for nanoelectronics ecosystem

OCTOBER 2012
III-V high mobility semiconductors for advanced CMOS apps

Yet another electronics policy for India?

IEF 2012: Turning recession into opportunity!

Global semicon sales to drop 1.7 percent in 2012?

Virtual prototyping ready for masses

MEMS to be $21 billion market by 2017: Yole

TSMC on 450mm transition: Lithography key!

SEPTEMBER 2012
Cadence Allegro 16.6 accelerates timing closure

Dr. Wally Rhines on global EDA industry

Solarcon India 2012: Solar industry in third wave!

AUGUST 2012
Apple wins big vs. Samsung in patent war!

Can being fabless and M-SIPS take India to top?

JULY 2012
Is Europe ready for 450mm fabs?

APRIL 2012
Xilinx intros Vivado Design Suite

MARCH 2012
Cadence releases latest Encounter RTL-to-GDSII flow

WLCSP market and industrial trends

FEBRUARY 2012
Top 10 semiconductor growth drivers: Intersil

Ingredients for successful fabless Indian semiconductor industry: Dr. Wally Rhines

Tariffs will slow growth in domestic demand for PV systems: The Brattle Group

Wireless leads in global semicon spends!

JANUARY 2012
India to allow imports of low-priced Chinese solar cells? Or, is it beaten?

Opportunities in turbulent PV equipment market

Ms. Fatima Toor, analyst, Lux Research, recently presented on opportunities in turbulent PV equipment market, in association with SEMI, USA.

Global PV market trends
Bankruptcies are galore. Eg. Solyndra, Abound Solar, Konarka, etc. Global trade wars are also on the rise. There are US tariffs on Chinese solar cells. There is also an EU investigation on Chinese solar panels. Then, there are Chinese investigations on US, EU and Korean polysilicon dumping. Government incentives have been lowered in the EU, but raised in Asia and Americas. Following Barack Obama's re-election in the US, the environmentalists are again upbeat about green energy.

Global PV demand increase will be driven by Asia and Americas in the coming years. Emerging markets will grow over six times in size from 2011-2017. Crystalline Si will be the dominant installed PV technology, at least till 2017. Gap between demand and supply will close.

The Q3-12 geographical capacity distribution would be across PV value chain. China leads in polysilicon, cells and modules supply. Chinese equipment manufacturers market share has been on the rise, ramping up competition for Western equipment suppliers.

Lux Research sampled 493 PV manufacturers. Of these, 40 percent are based in the EU, 28 percent are based in China, 17 percent are in the US and 15 percent are in the Rest of the World.

Opportunities for equipment manufacturers in current market state
Cost, efficiency and price are fundamental drivers of PV industry. Innovations across the value chain will enable higher margins for PV industry. The desire for cell and module manufacturers to reduce costs and differentiate will drive opportunities for equipment manufacturers.

Crystalline Si technology: Innovations across crystalline Si value chain would enable opportunities for equipment suppliers. Fluidized bed reactor (FBR) process requires 10 lWh/kg and is a continuous process. Why is FBR only 6 percent of total polysilicon capacity today? The reasons are:
* No off-the-shelf FBR reactors are available.
* Process complexity requires that Si granules can be polluted by impurities.
* There is an opportunity for equipment manufacturers to develop off-the-shelf FBR equipment that will enable reduced production costs for polysilicon.
* GCL announced developing its FBR technology.
* Samsung Fine Chemicals and MEMC have partnered to set up FBR polysilicon production due to its lower production costs.

Monocrystalline silicon (c-Si) ingot growth using Czochralski (CZ) method is high cost and results in pseudo-square c-Si wafers. Plate seed for qc-Si ingot growth with mc-Si grains on the edges and c-Si in the middle. ReneSola has technology with wafer capacity of 2GW of which 1.6GW is qc-Si Virtus wafers and 0.4GW are c-Si wafers. ReneSola is likely to be one of the Chinese companies to survive the shakeout due to its strategy and technology.

Opportunities exist to optimize qc-Si ingot growth. Modified directional solidification (DS) furnace makers claim 90 percent c-Si and 10 percent mc-Si yields during qc-Si ingot growth. In reality, 60 percent c-Si and 40 percent mc-Si results in high wafer binning and sorting costs. This provides an opp for equipment manufacturers to improve the c-Si yield to higher than 90 percent. The Qc-Si capacity is likely to increase in the coming years as DS furnace manufacturers innovate.

Global semiconductor industry outlook 2013: Jaswinder Ahuja, Cadence

How will 2013 turn out to be for the global semiconductor industry? Will there be growth for the global EDA industry? Importantly, how will the Indian semiconductor industry perform in 2013? I asked Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems India these questions.

Outlook for global semicon industry in 2013

First, how is the outlook for global semiconductor industry in 2013 going to be? Ahuja said: "The long term outlook for the semiconductor industry remains positive, with mobility and cloud computing being the key drivers. The global economy is forecast to grow around 4 percent annually through 2016, according to an April 2012 report from the International Monetary Fund (IMF).

"In its June 2012 report, Gartner predicted growth in electronics and semiconductor industries to outpace that of the world GDP growth, at 5½ percent annually to approach $2 trillion for electronics and 6 percent annually for semiconductors through 2016. So, the semiconductor industry outlook remains very positive overall.

"In the near term, multiple challenges will need to be weathered with respect to the global economic climate, especially in European markets. The JP Morgan/GSA Semiconductor Index of Leading Indicators points to a soft semiconductor industry in 2013. However, there are lot of new products in the mobile and tablet space that are driving demand, such as the iPhone 5, Microsoft Surface, and Samsung Galaxy S III.

"The China semiconductor space is emerging as a key market for semiconductor company revenue, and forecasts predict that it will show rapid annual growth rate. The consolidation and M&A activities that we are seeing in the global semiconductor industry also indicate a positive outlook for the upcoming year.

"In India as well, the semiconductor industry will continue to see growth. The injection of funds and other support outlined in the National Policy on Electronics will provide an impetus to home-grown design and manufacturing, which should start gaining traction in 2013."

Five trends for 2013
What would be the three or five trends likely to be visible in 2013? Ahuja said Cadence sees five big trends that will drive growth in the near and long term. These are: mobility, application driven design, video, cloud and security.

Probably, the most pervasive change in electronics recently has been mobility. When we talk about mobility, it’s just not about smart phones or tablets, but any kind of device which is mobile. Within the mobile space, software applications help system manufacturers and vendors differentiate themselves and stand apart from the competition. The need to have apps on all kinds of devices is driving rapid growth, as well as placing new demands on EDA companies.

The entertainment industry will be the key driver for video, and as the year progresses, we will continue to see more and more products and solutions introduced to tap into the demand. For the semiconductor industry, video will drive growth both in the end consumer market (mobile platforms) and the enterprise space (networking industry).

In many ways, the backbone to mobility is the cloud. With its network servers and infrastructure, the cloud is what delivers much of the content and value to all of those mobile devices. Statistics show that we need one server for every 600 smart phones and one for every 120 tablets. So there is a big need for data centers which can provide support for all the computing and back-end operations.

Security of data in mobile devices and the cloud will continue to be a challenge in the near future. There will be renewed calls to develop products that can protect critical infrastructure and sensitive information from security breaches.

Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design has seen growth from RF/analog design and simulation, and analysis As design methodologies mature, EDA expenditures stop growing. He was speaking at Mentor Graphics' U2U (User2User) conference in Bangalore, India.

Most of the EDA revenue growth comes from major new design methodologies, such as ESL, DFM, analog-mixed signal and RF. PCB design trend continues to be flat, and includes license and maintenance.

The IC layout verification market is pointing to a 2.1 percent CAGR at the end of 2011. The RTL simulation market has been growing at 1.3 percent CAGR for the last decade. The IC physical implementation market has been growing at 3,4 percent CAGR for the last decade. Growth areas in EDA from 2000-2011 include DFM at 28 percent CAGR, formal verification at 12 percent, ESL at 11 pecent, and IC/ASIC analysis at 9 percent, respectively.

What will generate the next wave of electronic product design challenges, and the future growth of EDA? This would involve solving new problems that are not part of the traditional EDA, and 'do what others don't do!

Methodology changes that may change EDA
There are five factors that can make this happen. These are:
* Low power design beyond RTL (and even ESL).
* Functional verification beyond simulation.
* Physical verification beyond design for manufacturability.
* Design for test beyond compression.
* System design beyond PCBs

Low power design at higher levels 
Power affects every design stage. Sometimes, designing for low power at system level is required. System level optimization has the biggest impact on power/performance. And, embedded software is a major point of leverage.

Embedded software has an increasing share of the design effort. Here, Mentor's Nucleus power management framework is key. It has an unique API for power management, enables software engineers to optimize power consumption, and reduces lines of application code. Also, power aware design optimizes code efficiency.

Functional verification beyond RTL simulation
The Verification methodology standards war is over. UVM is expected to grow by 286 percent in the next 12 months. Mentor Graphics Questa inFact is the industry’s most advanced testbench automation solution. It enables Testbench re-use and accelerates time-to-coverage. Intelligent test bench facilitates linear transition to multi-processing.

Questa accelerates  the hardware/software verification environment. In-circuit emulation has been evolving to virtual hardware acceleration and embedded software development. Offline debug increases development productivity. A four-hour on-emulator software debug session drops to 30 minutes batch run. The offline debug allows 150 software designers to jumpstart debug process on source code. Virtual stimulus increases the flexibility of the emulator. As an example, Veloce is 700x more efficient than large simulation farms.

Physical verification beyond design for manufacturability
The Calibre PERC is a new approach to circuit verification. The Calibre  3DSTACK is the verification flow for 3D.

Global medical image sensors market to grow 64 percent by 2017

The global market of medical image sensors will grow from $68 million in 2011 to $112 million in 2017, a growth of 64.7 percent. Whereas the contribution in value of the global endoscopy market represents only a few 10 percent of the medical image sensors market in 2011, 90 percent is related to x-ray applications. These are some of the conclusions drawn by Benjamin Roussel, technology and market analyst - MedTech, Yole Développement, France, in a seminar on how CCD, CMOS and a-Si are reshaping the global medical imaging market.

He added that image sensor innovations are reshaping the medical imaging industry as it permit the entry of news market players, the development of news products in line with both patient and physicians requirements. The medical image sensors market is currently evolving. Emerging technologies are expected to go mainstream in the future, fueled by new applications with high growth rates.

Image sensor technologies overview
Comparing CCD vs. CMOS architectures, CCDs move photo-generated charge from pixel to pixel and convert it to voltage at an output node. CMOS imagers convert charge-to-voltage directly inside each pixel.

As for a-Si flat panels, electrons are accumulated in photodiodes and then transferred by switching a thin-film transistor addressed by a line pulse. The signal is readout by an external amplifier and analog-to-digital converter.

X-ray and endoscopy apps
Medical applications are vast and numerous, such as microscopy, endoscopy, x-ray based methods, MRI, ultrasound imaging and nuclear medicine.

Medical image sensors are integrated into larger products -- medical devices. Depending on the market the medical device aims for, the image sensors functions change. For example, while power consumption is critical for camera pill devices, for reusable endoscopes it’s temperature and humidity resistance.

The objective of the segmentation is to organize the medical image sensors market into well defined segments. Each one of those have their own drivers and set of requirements, and identify which applications present a real opportunity for micro-system technologies. X-ray image sensors price are, on average, 1,000 times larger than endoscopic image sensors.

Dynamics of image sensors
The global medical image sensor market will grow from $68 million in 2011 to $112 million in 2017. The global medical image sensors market in volume will grow from 1.4 Munits in 2011 to 4.6 Munits in 2017, fueled by emerging endoscopy products: camera pills and disposable endoscopes.

The CCD medical image sensors market dedicated to endoscopy will grow from $4 million in 2011 to $5 million in 2017. In parallel, the total CMOS medical image sensors market will continue to grow sharply from $1 million in 2011 to $3.5 million in 2017.

The medical IS market for x-ray application will grow from $63 million to $103 million in 2017. The CMOS x-ray image sensors revenue will continue to grow at a 12 percent CAGR 2012-2017 and reach $44 million in 2017.

Future perspectives
Medical image sensors technology is the gateway for new entrants in endoscopy market. CMOS camera, 3D imaging and multispectral are the three different trends that will shape the future of endoscopes.

Likewise, the current move to CMOS, the move from indirect to direct conversion of x-ray (no scintillator, no fiber optic plate), and the move toward single photon detectors are the trends likely to shape the future of x-ray systems.

New sapphire apps can trigger an investment cycle!

Too many new entrants on sapphire for LED market with unrealistic capacity plans. Most underestimated the technical challenges! Prices are likely to remain low through 2013. Many new entrants will fail in 2013-2014: rationalization (M&A, bankruptcy, attrition). In the long term, vertical integration is desirable to avoid margin stacking, said Eric Virey, senior market and technology analyst, LED Materials and Sevices, Yole Developpement. He was presenting a seminar on how new sapphire applications can trigger an investment cycle.

According to him, adoption of CFL and LED stretches the replacement cycle and cannibalizes lamp volume sales. As for LED manufacturing capacity, with respect to nitride MOCVD reactors, 2009 and 2010 saw increases in Taiwan and Korea in late driven by LCD display market. The years 2010-2012 saw phenomenal increase in China. Government subsidies are likely to build up epitaxy capacity in the mainland, which should be more than $1.5 billion.

Currently there are ~110 companies with epitaxy capacity. Many will likely disappear! The current excess MOCVD capacity will be fully absorbed by mid-2014. The MOCVD reactor installation will resume mid-late 2013. The global MOCVD utilization rate is 61 percent. There is wide variability between leaders and tier 2 players in China. The Q4-2012 LED sapphire consumption was worth 3.9 million two inch equivalent per month.

As for companies in sapphire wafer, 130+ companies are involved in the sapphire substrate (established or development stage). Less than 30 currently are deriving meaningful revenue from LED substrates. The capacity is ~80 percent higher than demand. It could get worse in 2013! Prices are likely to remain low. Many new entrants will disappear, and others will scale back. A few will succeed.

Conditions for survival through 2013 include, having a lot of cash, be qualified in supply chain, achieve <$4/mm cost (2” basis), and serving other market could be a plus.

As for wafer price trends, the finished wafers following similar trends. The 6” is now offered for <$200, but price can vary significantly based on specifications. There are said to be simulated 4” core cost structure for various manufacturers.

FPGA design heads to the cloud!

Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company's go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.


Since pay-as-you-go business models are rare in the semiconductor industry, Plunify went through several steps, of which the first was to better understand the market, the available tools and stake-holders.

* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?

With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns - security, accessibility and cost.

"Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market," he added.

How can the on-demand cloud computing platform dramatically accelerate chip design workflows According to Harn Hua Ng, one immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in 3 months' worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.

Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).

With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.

Status of power semiconductor devices industry

There are more available solutions than ever in power devices, according to Alexandre Avron, market and technology analyst, Yole Développement. The landscape is moving, and its moving quite fast, from every region of the world.

There are many opportunities for power device manufacturers. This is the time for strong strategic planning and making the best choices. He was speaking at a seminar on the power semiconductor devices industry, in Lyon, France.

IGBTs and SJ MOSFETs
Silicon is not dead and will still live for a long time. Standard device design are slowly disappearing (planar IGBT, planar MOSFET). IGBT and SJ MOS are highly mature technologies. Rules of competition are evolving as well.

Historic players need to keep on innovating. New entrants have a different business model: there are more and more foundries, with fab-less and fab-light players. IGBT is still a key asset: master and secure IGBT supply is necessary for system makers. SJ MOSFETS will be used in more and more systems, taking market shares to planar MOSFET.

About SiC and GaN, there is still a big question mark: Where and when? With time, it is becoming clearer. SiC will target medium and high power. From our point of view, medium power (1200V base) is a mean to arrive to high power (+3.3kV). R&amp;D has to go through this to reach higher voltage. The main issue is still on current ratings (having a high impact on cost).

GaN will target low and medium power, and will probably allow extraordinary power supplies designs (Tiny supplies, very high frequency systems). It is almost ready for 600V, but not yet at 1200V. It leaves room for SiC to develop and expand.  Major players are involved on both fields — SiC and GaN. They need to be present on both domains, as there will be an overlap, but the split is unclear: we will probably experience a very fine segmentation, not only by voltage or current, but also by frequency, ruggedness, system size, temperature of operation or maybe culture or history.

SiC is now here. First full SiC PV inverters are available. First field tests for SiC in rail traction is ongoing. GaN is under qualification. According to the most advanced players, 600V GaN devices samples are tested by system makers.

Sonics in TSMC's Soft IP Alliance 2.0 beta program

Milpitas, USA-based Sonics Inc. recently participated in TSMC’s Soft IP Alliance 2.0 beta program. Driving high quality soft IP eases customer integration and expedites the time-to-market.

Sonic's role in TSMC beta program
Speaking on the beta program and Sonics' role, Frank Ferro, director of Product Marketing, Sonics, said: "TSMC's Soft IP kit 2.0 beta program is part of TSMC’s Open Innovation Platform program that creates a complete ecosystem for customers with the overall goal of shortening design time. This is done by providing a large catalog of partner provided IP that is silicon-verified and production-proven.

For vendors like Sonics, TSMC has extended this ecosystem to include Soft-IP (IP not designed for a specific process, but delivered as RTL). The program allows Soft-IP partners to access and leverage TSMC's process technologies to optimize power, performance and area for their IP.

IP cores are checked through TSMC’s foundry checklist to ensure the customers have optimized design results with fast IP integration built into their design. This flow also facilitates easy IP reuse for subsequent designs. The soft IP Kit beta 2.0 program is an extension of the current program through implementing additional quality checks, improving results and making the flow easier for customers to use.

There are several advantages to Sonics as a participant in this program. First, customers of TSMC will have access to Sonics IP through TSMC’s IP library. Given TSMC’s strong market share, this will allow Sonics IP to be visible to a large customer base. In addition, TSMC’s customers will feel securing using Sonics IP because they know that it has been put through a rigorous series of IP checks that meet the highest quality standards. It also allows Sonics early access to TSMC’s process libraries, allowing Sonics to optimize performance and area for each IP product.

So, what can the TSMC's Soft IP Kit 2.0 do? How does Sonics enhance its capabilities? The Soft IP Kit 2.0 provides a specific RTL design flow methodology and hand-off which includes: lint (RTL coding consistency), clock domain crossings (CDC), power (CPF/UPF), physical design (routing congestion), design for test (DFT), constraints and documentation.

Using this flow enhances Sonics IP quality and reliability because many RTL errors can be caught at an early stage. As mentioned above, this flow ensures lowest power and best performance of the IP for a given process node.

Global solar PV industry to remain under pressure in 2013!

The outlook for the global solar PV industry does not look encouraging, at least, if recent happenings are set as benchmark. How will the global solar PV industry perform in 2013? How will the modules segment perform? How will solar cells segment perform in 2013?

Dr. Henning Wicht, director and principal analyst Photovoltaics, IHS iSuppli, said: “The industry will remain under pressure. We expect prices to decline further on all nodes. Margins will remain thin. Cell production outside of China, in particular Taiwan, can benefit from US anti-dumping tariffs on Chinese modules.

“However, Taiwanese cell producers will face difficulties, since European customer base will shrink. Module production will remain challenging. Prices are expected to decline further due to overcapacities and fierce competition.” Here is a graph of the module price decline.

There are a few other questions. Did the global solar PV industry touch 22 GW in 2012? What is the prediction for 2013? Also, how is Japan doing? Are we seeing pro REE politics there?

Dr. Wicht said that IHS iSuppli expects 31 GW of new installations in 2012. For 2013 IHS iSuppli forecasts 35 GW. “Installations in Europe are declining, while installations in emerging markets and Asia are increasing. China, US and many of the new markets favor ground installations. Europe and Japan address more rooftops. Japan has been seeing a lot of activities in H2-2012. We expect this boom to continue into 2013.

“IHS expects that the Japanese government will adjust tariffs in 2013, since investment conditions are very generous. This is helpful to kick-start the market. However, the generous tariffs will become expensive for rate payers if maintained too long. Details on tariff adjustment are not yet defined.”

Finally, how will the industry focus on electricity storage and grid integration in 2013? And, what’s going to happen with Chinese suppliers in 2013?

Dr. Wicht replied: “Solar companies will see continuing and even increasing difficulties during 2013. Thin margins for all producers (including silicon) will maintain. Smaller players will stop production. Also 2nd and 3rd tier Chinese suppliers will partially stop production. Tier 1 Chinese players will face difficulties of financing if stock prices will not increase and companies will be excluded of Nasdaq (pending).

“Also, anti-dumping investigations in Europe can harm Chinese module business in 2013 since buyers will be careful to avoid any retroactive tariff from beginning of 2013. Strategy wise, 2013 will be a very difficult year. Electricity storage is an emerging topic, which is now addressed mainly by inverter suppliers. Grid integration of PV power is becoming a concern of EPCs and investors.”

Netronome and Argon Design launch Blaster flow simulation solution

Argon Design, a leading developer of high performance software applications for manycore communications processors, launched Argon Blaster, the industry’s first flow simulation solution for generating realistic, Internet scale traffic loads and applications to test networking and security equipment.

Blaster delivers a line rate, timing accurate, flow simulation application on an affordable PCIe acceleration card for use in standard x86 platforms. This enables OEMs to cost effectively distribute a high performance simulation and traffic generation solution throughout the engineering organization. The approach significantly reduces development time and cost, while simultaneously increasing product quality.  

Blaster is designed for enterprise and carrier network operators for performance testing of flow based cyber security and network analytics applications. It enables network managers to verify that these systems are designed and deployed in a manner to match expected network loads.

Elaborating on the features, Daniel Proch, director of product management, Netronome, said: "Argon Blaster is the industry’s highest-performance and most-accurate flow simulation solution, in an affordable package. Developed by Argon Design, Blaster enables a standard x86 PC with a Netronome flow processor PCIe card to generate realistic, Internet-scale traffic loads and application mixes. 

"For many networking applications, the ability to classify and manage traffic flows is key to enabling the highest level of performance and scalability. Quality of Service, Load Balancing, Firewall, Intrusion Detection, Content Inspection, Data Loss Prevention and similar applications all typically require flow-aware processing capabilities and this flow-aware traffic generation solution for development and QA. 

Blaster is the first traffic generation tool designed specifically for flow simulation applications. With Blaster, you can emulate up to a million unique flows with accurate, consistent, per-flow rate control.

It will be interesting to know how Blaster will help the ISVs and OEMs generate realistic, Internet-scale traffic loads and applications to test networking and security equipment.

Blaster can be installed in any modern PC running Linux. It installs as a KVM virtual machine and can be operated from within the virtual machine or externally. It replays one more multiple .pcap files and can take that traffic and emulate any type of traffic profile from that pcap(s). The user can change the # flows per pcap file, the addressing scheme (# clients and servers based on MAC and or IP address). 

From this set of knobs and given a set of pcaps with appropriate application traffic to any traffic load and application mix that is desired. Organizations can then offer:

* Performance benchmarking to isolate bottlenecks.

* Stress testing with real-world loads.

* Security testing with background, application and attack traffic.

* Quality assurance with broad spectrum of application and protocols.

 

Let's find out a bit more about the role played by Netronome as well as Argon Design. Pooch said: "The product is an Argon branded product that is a joint development with Argon Design. Netronome provides the accelerated flow processing hardware for the solution in the form of a standard PCIe card, and Argon designed and engineered the software. Netronome will be handling sales and marketing of the product. Software and support will be handled by Argon."

 

Will there be an upgrade sometime later, next year, perhaps? "Most certainly," continued Pooch. "Our early access customers and internal use has already developed a robust roadmap and we anticipate these features and others to be rolled out over several subsequent software releases. We also expect to have a new hardware version based on our recently announced NFP-6xxx family of flow processors when available."

Dr. Wally Rhines on global semiconductor industry outlook 2013

It always gives me great pleasure chatting with Dr. Walden (Wallly) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA. 2013 is just round the corner. What lies ahead for the global semiconductor industry is a question on everyone's lips! How will the EDA industry do next year? For that matter, what should the Indian semiconductor industry look forward to next year?

Three trends for 2013
First, I asked Dr. Wally Rhines regarding the trends in the global semiconductor industry. He cited:

* Growth in communication ICs.
* Growth in the third dimension.
* Accelerated design activity at the leading edge.

Growth in communication ICs: On the macro level, silicon area shipments continue to grow gradually, as do semiconductor unit shipments. However, there’s a major shift in application segments from computing to communications. Communications used to be only one third the size of computing in terms of semiconductor usage.

Communications are expected to surpass computing in terms of semiconductor consumption by 2014 thanks to the rapid growth of wireless applications, the incorporation of computing into communications devices like smart phones and the addition of communications to computing devices like tablet computers.

Growth in the third dimension: Shrinking feature sizes and growing wafer diameters will continue to contribute to the annual 30 percent decrease in the average cost per transistor and average 72 percent unit growth of transistors, but they will do so at a diminished rate. Fortunately, other avenues are emerging that can help sustain the semiconductor industry’s remarkable rate of growth. One largely untapped opportunity is in the third dimension, i.e. growing vertically instead of shrinking in the XY plane.

DRAM stacks of eight or more die are already possible, although they are still more expensive on a cost per bit basis compared to unstacked devices. Complex packaged systems made up of multiple heterogeneous die, memory stacked on logic and interposers to connect the die are evolving rapidly. Layers in the IC manufacturing process continue to increase as well.

Accelerated design activity at the leading edge: Another interesting trend is the recent surge in capital spending among foundries to add capacity at the leading edge. This wave of spending will result in excess capacity, at least initially, which may force foundries to lower prices to boost demand. In fact, capacity utilization data in the last few months shows a dramatic decline in utilization at 28/32nm and 22nm nodes, suggesting that excess capacity is already happening to an extent.

While differences in 28 and 20nm processes—such as double patterning—create challenges, the existing capital equipment is largely compatible with both processes. Such a high volume of wafers and the large available capacity will lead to increasingly aggressive wafer pricing over time. As a result, cost-effective wafers from foundries will encourage totally new designs that would not have been possible at today’s wafer cost.


Industry outlook 2013
So, how is the outlook for 2013 going to shape up? Dr. Rhines said: "After almost no growth in 2012, most analysts are expecting improvement in semiconductor market growth in the coming year. Currently, the analyst forecasts for the semiconductor industry in 2013 range from 4.2 percent on the low side to 16.6 percent on the high side, with most firms coming in between 6 percent and 10 percent. The average of forecasts among the major semiconductor analyst firms is approximately 8.2 percent.

"However, most semiconductor companies are less optimistic in their published outlooks. This seems to be influenced by the level of uncertainty that exists because of unknown government actions and market conditions in the US, Europe and China."

Any more consolidations?
It would be interesting to hear Dr. Rhines' opinion on any further consolidations within the industry. He said: "It is common misperception that the semiconductor industry is consolidating. A closer look at the data shows that the semiconductor industry has been doing the opposite. It has been DE-consolidating for more than 40 years.

"Take the #1 semiconductor supplier, Intel. Intel’s market share is the same today as it was a decade ago. And, the combined market share of the top five semiconductor suppliers has been slowly declining since the 1960s. Similar trends also apply to the top ten and top 50—both are the same or lower than they were a decade, as well as decades, ago. In fact, the combined market share of the top 50 semiconductor companies has decreased 11 points in the last 12 years.

Focus on monolithic 3D-ICs paradigm shift for semicon industry

MonolithIC 3D Inc. was established in 2009 by Dr. Zvi Or-Bach, a well-known Silicon Valley serial entrepreneur, as NuPGA. The NuPGA's mission was to develop programmable logic technology with density, speed, and power approaching ASICs.

On the way, while developing improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D-ICs. Recognizing that this breakthrough and its many related innovations represented a paradigm shift for the entire semiconductor industry, Dr. Zvi Or-Bach changed the strategy to focus on monolithic 3D-ICs, and renamed the company MonolithIC 3D Inc.

Monolithic 3D is based in San Jose, California, USA, where I met Dr. Zvi Or-Bach, president and CEO.
First, I asked him to elaborate on the technology breakthrough that allows the fabrication of semiconductor devices with multiple tiers of copper connected active devices utilizing conventional fab equipment.

Dr. Zvi Or-Bach said: "The challenge is that once interconnect made of copper (or aluminum) is in that wafer should not be process at higher than 400 degrees C. The common view is that forming single crystal transistors would require higher than 1,000 c. The common view is that forming transistor in monocrystalline silicon layer require higher than 800 c. MonolithIC 3D's innovation is finding path to overcome the above challenge utilizing monocrystalline silicon layer and conventional fab equipment."

MonolithIC 3D offers solutions for logic and memory technologies, with significant benefits for cost, power and operating speed. The benefits for logic is detailed in Monolithic's blog: Is the Cost Reduction Associated with Scaling Over?

Monolithic 3D provides the equivalent of one node of scaling for every folding at fraction of the development and equipment costs. And, it provide additional benefits such as:
* Significant advantages for using the same fab, design tools.
* Heterogeneous integration.
* Process multiple layers together Nx cost improvement.
* Logic redundancy => 100x integration.
* Enable modular design.

Dr. Zvi Or-Bach added: "The benefits for memory is that allow processing multi-layers of  single-crystal memories at comparable lithography cost of single layer. As of today, lithography costs dominate process costs than monolithic 3D allow future scaling at ever reduce costs and higher memory capacity."

The company believes in collaboration with existing players in the semiconductor industry. MonolithIC 3D is not an IC producer, but rather, a technology innovator, who also file many patents which are available to be license by all industry players. Monolithic has been assigned a patent (8,294,159) developed by five co-inventors for a "method for fabrication of a semiconductor device and structure.  In fact, MonolithIC 3D has now been 20 granted patents of which 20 had been already issued.

PS: I am extremely grateful to Dr. Tim Majumdar, senior RF engineering manager and inventor,  who pointed me to this company.

Xilinx announces 20nm portfolio strategy

Xilinx Inc. has announced its 20nm portfolio strategy. The 20nm portfolio will allow Xilinx to offer twice the performance at half the power. It will increase productivity by 4x, and improve integration by 1.5- 2x. Besides, there will be 20-50 percent lower BOM cost.

Xilinx's 20nm all programmable portfolio builds on 28nm breakthroughs to stay a generation ahead. "At 20nm, we were able to break out to become an all programmable company," said Neeraj Varma, country manager, sales, India, Australia and New Zealand, Xilinx India.

The next generation FPGAs, second generation SoCs and 3D ICs will be ‘co-optimized’ with Vivado for the most compelling alternative ever to ASICs and ASSPs. From enabling programmable logic, the Xilinx 20nm portfollio will enable programmable systems integration!

The first SoC strength design suite was shipped in Q2-2012. It has been built from ground up for the next decade of all programmable devices. Today, the Xilnix Vivado is used for over 30 percent of 28nm FPGAs and 100 percent for 3D ICs.

Xilinx has been expanding on its next generation competencies. The 3D IC expertise and supply chain has gone from homogenous to heterogenous. The SoC and embedded software has also undergone change, as have XCVRs and analog mixed signal (AMS), communications BU and applications IP, and next generation design automation. Xilinx is now charting an aggressive course forward.

Xilinx's 20nm portfolio has been co-optimized for performance, power and integration to address the market needs at 20nm. For the next-generation FPGA,, it will provide unmatched system optimized transceivers at highest channel quality w/ second generation auto equalization. There will be higher bandwidth w/over 100 transceivers @ 33Gb/s.

Elliptic intros world’s first commercial touchless gesturing technology!

Palo Alto, US-based Elliptic Labs has introduced the world’s first commercial touchless gesturing technology using ultrasound, designed for electronic devices and Windows 8. Elliptic’s breakthrough technology is the first of its kind commercially available and has been incorporated in the Windows 8 Gesture Suite, introduced today. So, what’s this new technology from Elliptic Labs really all about?

Well, OEMs now have a commercially available technology to integrate gesture recognition in their terminals – with extremely low power and robust detection of hand gestures. The technology is based on ultrasound, and requires a small number of low-cost components (microphones, transducers) for integration in the terminal.

The actual gesture recognition is done on the host CPU, running a power-efficient detection software provided by Elliptic labs. Ultrasonic gesture recognition has a perfect fit with Windows 8 user interface, and the company provides gestures for very simple interaction with a Windows 8 terminal with the new Modern/METRO user interface.

With this technology, you can command a laptop simply by gesturing in front of the computer, and to the sides and above the screen. A key feature of ultrasound is that Elliptic Labs supports gestures not only in the front of the computer, but also to the sides and above, enabling intuitive interactions with the terminal.

Another advantage of ultrasound is that it works in complete darkness, and in direct sunlight, which is challenging for camera-based solutions, and very important for mobile use. Yet another great news is the availability of a Software Development Kit (SDK), so that the OEMs and ISVs can adapt the technology to their particular applications. To make it very simple to get started, Elliptic Labs has provided a Starter Kit to get started with ultrasound gestures in minutes.

Mobiles and tablets groove!

This technology can also be used in laptops, mobiles and tablets. A Windows 8 laptop can be operated by simple gestures, which is usually found on touch screens. The OEMs and ISVs can now create new and intuitive user interfaces for a Windows 7 or Windows 8 computer as they wish.

With the SDK, game developers can quickly port their games to support ultrasound controls, and business applications can leverage gestures for quick browsing, selection, and general operation of software. Mobiles and tables can also leverage ultrasound gestures, as the SDK is being made available also for the Android operating system.

Ultrasonic approach!

Elliptic Labs has made use of the ultrasonic approach, which apparently, makes life easier for batteries. The amount of information from a few microphones is much smaller than the amount of information from camera-based solutions. The algorithms for ultrasound gesture recognition can execute with less instructions, resulting in significant lower power usage.

As a result, the ability to do gesture recognition can be “always on”, so users can rely on gestures for all applications of the terminal. The aspect of power consumption is of particular importance for mobile terminals.

Elliptic is a leader in ultrasonic touchless gesturing for consumer electronic devices. Its patented, low-power, responsive new technology is superior to the limited, camera-based approaches on the market. The Windows 8 Gesture Suite enables a touchless version of all touchscreen gestures in the new operating system. Combined with Elliptic’s SDK, the technology gives OEMs the flexibility to create disruptive new ways to interact with devices.

Elliptic’s ultrasound technology uses sound waves and microphones to detect movement, similar to how radar detects objects. The technology is not limited to detecting movement within camera view — it detects natural hand movements that extend beyond the camera, surrounding a device screen.

Global semicon industry outlook 2013: Analog Devices

What does 2013 have in store for the global (and Indian) seniconductor industries? Will it do better than 2012 or will it be even? I had a chat with Somshubhro Pal Choudhury, managing director, Analog Devices India Pvt. Ltd recently on this subject. First, I asked about the trends in the global semiconductor industry.

Industry trends
Choudhury said: "Consumer and telecom have driven the growth incessantly for the past decade for the semiconductor industry and will continue to do so. Over the next three years, industry analysts estimate the global industry will grow approximately 6 percent 2013-2016 CAGR.

"Portability and wireless connectivity will continue to drive a significant portion of the industry growth. Increasingly, automotive market is becoming very lucrative as the quantity of electronics going inside automobiles is increasing phenomenally in safety, power train, smart vision and fuel efficiency applications, not to mention the use of wireless connectivity.

"Medical electronics is getting smaller, smarter with better diagnostic technologies while the demand is increasing with aging population, increased longevity and lifestyle oriented diseases. Applications such as in-home patient monitoring will use wireless connectivity to stay in contact with physicians and emergency services.

"Industrial automation, energy and defense sectors are growing with more factory automation, solar energy focus worldwide, electronic warfare and so on. Intelligent, connected, and energy-efficient systems are leading to higher electronics content, with sensors and motors distributed throughout the industrial complex being connected wirelessly.

"Finally, the wireless and wired networks that transmit and receive all these channels of data will be a major driver of growth over the next few years with proliferation of 4G and increasing amount of fiber."

Outlook for 2013
How is the outlook for 2013 going to shape up? What are the technologies likely to make an appearance and why?

According to Chowdhury, the 4G LTE deployment should be a major applications area driving 2013. To that end RF, high-speed signal processing, and power management will be important technologies to advance the price/performance of 4G networks. MEMS technology continues to find new applications in medical, defense and industrial applications over and beyond the tablets, handsets, gaming consoles and airbag sensors in cars.

Will there be further consolidations within the industry? He added that M&A will continue to play a role in the industry. The companies in the industry are not hampered by their financial abilities to acquire businesses, but identifying complementary opportunities and successfully integrating them is not without risk.

And how does the global EDA industry look like doing in 2013? As per Choudhury, the EDA industry continues to innovate and that pace will continue in 2013. These innovations are not only driven by the challenges of moving to the next node, but also for mixed signal designs, in analog-digital co-simulation and verification domain.

ReneSola intros Virtus II PV modules in India

ReneSola Ltd, a leading global manufacturer of solar PV modules and wafers, has introduced its new Virtus II multicrystalline modules in India. ReneSola has started providing locally produced PV modules to the Indian market and expects to provide 250 MW of India-made PV modules over a two-year period.

The India launch follows the successful introduction of the Virtus II solar modules to the US and Australian markets.

Founded in 2005, Renesola has 17 subsidiaries worldwide. Production sites located in Zhejiang, Jiangsu and Sichuan, China. The supplier estimates to ship 1,550 ingots and 700 wafers during 2012, up from 1,014.1 ingots and 295,2 million wafers in 2011.

Some of Renesola's projects include 4MW and 2MW in Slovakia, 11.5MW in Germany, 20MW in China, 9.21MW in Italy, and 27.6MW again in Germany. A couple of Renesola's rooftop projects include 118.8KW in Slovakia, 1.95MW and 100.8KW in Greece, 1.4MW in Belgium, 12.96KW in Bulgaria, and 806.4KW in Germany.

Virtus II modules
Characteristics of the Virtus II modules include higher power output, higher performance at same cost, same LID, and same CTM cost. Virtus ingot improves the distribution of grain size and lifetime, and provides higher lifetime and lower dislocation density. The Virtus A++ wafer allows uniform grain distribution with less defects. The Virtus A++ wafer also has much lower defects.

Major defects of conventional multi‐crystalline wafers can be reduced by the innovative controlled DSS method. The Virtus I module provides better temperature coefficient of power and lower light induced degradation compared to mono modules. The Virtus II wafer increases cell efficiency due to higher lifetime, lower dislocation and uniform grain size. The Virtus II module shows better performance and the same production cost of multi-module.

IMEC’s 450mm R&D initiative for nanoelectronics ecosystem

Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&amp;D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&amp;D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.

IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&amp;D pilot line will enable full 450mm process capability for advanced nodes by early 2017.

Scaling
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture. Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.

IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.

IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.

With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.

III-V high mobility semiconductors for advanced CMOS apps

Clement Merckling, imec, Belgium, presented on the epitaxial growth and in-situ passivation requirements for III-V high mobility semiconductors for advanced CMOS applications at the Semicon Europa in Dresden, Germany.

The motivations for III-V MOS transistors include higher electron carrier mobility (@ low-field), more efficient source injection, smaller energy bandgap, VDD scaling, band engineering capabilities, lower temperature processing, high-K gate first process possible and 3D compatible architecture.

The International Technology Roadmap for Semiconductors (ITRS) believes in Ge and III-V. IMEC epi + in-situ oxide 'tool park' involves MBE (molecular beam epitaxy) and MOVPE (metalorganic vapour phase epitaxy) III-V growth techniques. The III-V EPI is clustered with in-situ oxide capabilities.

The AIXTRON Crius 300mm looks at III-V selective epitaxial growth (III-As and III-P). The AMAT/RIBER III-V logic cluster 300mm looks at the III-V selective epitaxial growth (III-As and III-P), in-situ surface analysis, handled by RIBER ISA 300, and oxide (ALD and MBE) chambers in-situ.

The RIBER MBE 49 cluster 200mm looks at the III-V solid source epitaxy (III-As and III-Sb) oxide chamber in-situ.

Main issues and challenges
Main issues for III-V integration include III-V integration on Si platform. There are all sorts of crystalline defects. Next, gate stack formation on MOS. It is much more difficult to passivate interfaces. Smaller bandgap, means, an increased Ioff due to band-to-band-tunneling.

Challenges with III-V heteroepitaxy on Si include Lattice mismatch, anti-phase boundaries (APB), mismatch stress relaxation and related defects such as dislocations at interface, and extended defects (threading arms, SFs). There are other defects caused at isolation interfaces, such as twins, stacking faults, facets, etc. Finally, there is interdiffusion at heterogeneous interfaces.

However, it is possible to achieve high quality heteroepitaxy by direct epitaxy using metamorphic buffer and defect confinement and wafers bonding. Strain relaxed buffer (SRB) is among the options for III-V materials integration at imec.

There can be InGaAs metamorphic buffer, with the MBE growth of low defect density and device quality III-V heterostructure using a suitable metamorphic buffer. Or, there can be III-Sb on Si by SS-MBE, that provides a route to relax III-V.

Defect confinement is possible via 'necking effect'. The selective area growth (SAG) of III-V compounds via MOVPE (or CBE ?) means the defects are trapped at trench edges. The other way is dislocation trapping in narrow STI trenches for aspect ratio >2. There is low defect density material in the upper part of the trench.

Elimination of APBs for on-axis Si (001), Si recess engineering, is possible either via rounded-Ge surface or V-grooved surface. In the rounded-Ge surface, step creation is done by surface engineering of a Ge seed layer. Double steps on a Ge surface are more stable and easy to form with a lower thermal budget than on Si.

In V-grooved surface, (111) surface is obtained either by KOH or TMAH wet etching. Growth inside a pre-defined Si {111} enclosure promote initial III-V nucleation uniformity.

The 'necking effect' approach presents its own challenges. One, perpendicular view, where there is efficient defect necking effect with side wall and parallel view, which allows viewing high defect density.

Yet another electronics policy for India?

India has once again announced an Electronics Policy, and frankly, I’ve lost count, how many times! Nevertheless, one hopes that this policy somehow takes off, and helps India get off the ground!  There are certain points in the policy that are worth a relook.

One, the setting up of electronic manufacturing clusters. This has been time and again stressed and re-stressed. Will it come around, this time? Let’s wait and watch, if it happens this time!

Two, as per the policy, there is a proposal for setting up two semiconductor wafer manufacturing fabrication facilities. Where? As far as one knows, there is hardly any infrastructure around to support even one semicon fab! Some people may say, Bangalore, but well, they are welcome to say that! As for people buying more of ‘domestically manufactured electronic goods’, it remains to be seen!

Three, back in 2007, when the SIPS program was announced, there were great expectations! If you recall some time ago, I mentioned that the Indian semiconductor policy, announced back in 2007, had supposedly expired on March 31, 2010! Then, the Indian industry came up with recommendations that included extending the Indian semicon policy up to March 2015! So, what happens to that? Or, is it dead and buried?

Four, back in 2007, the ‘ecosystem units’ were clearly defined as units, other than a fab unit, for manufacture of semiconductors, displays including LCDs, OLEDs, PDPs, any other emerging displays; storage devices; solar cells; photovoltaics; other advanced micro and nanotechnology products; and assembly and test of all the above products. What’s happening now?

Five, does all of this mean that the role of India-based semiconductor companies as a percentage of the semiconductor market globally, will improve? Or, do we take India as a system/gadget maker and thus, as a percentage of that market??

Six, fabrication is increasingly expensive, much involved and the actual global fabrication players are declining and will be about three to four companies. There is talk of 450mm fabs across the world! Have we even heard a word from India?

Okay, so let’s say, India will have two fabs? By when? What process technology? If it is a 450mm fab, India can very well kiss goodbye to this decade, at least. And, India continues to slip back in having a ((proper) fab!

IEF 2012: Turning recession into opportunity!

Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:

Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.

Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.

With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.

John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.

This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.

These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.

Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.

Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.

As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.

Global semicon sales to drop 1.7 percent in 2012?

This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.

According to the WSTS’s August (posted Oct. 9th, 2012 on its website) actual global semiconductor sales of $23.013 billion, the updated monthly forecast expectation for full year 2012′s total global semiconductor sales is expected to be $294.6 billion as calculated by the Cowan LRA forecasting model.

This latest update to the 2012 sales forecast estimate corresponds to a year-over-year sales growth expectation of minus 1.7 percent, which dropped from the previous month’s year-over-year sales growth forecast estimate of minus 0.5 percent.

It is also lower than the joint WSTS/SIA Spring 2012 sales growth forecast (published in June of this year) of plus 0.45 percent which corresponds to a global sales forecast estimate of $300.9 billion. Therefore, the model’s latest monthly sales forecast output (based on the just announced August 2012’s actual sales) continues to project even more negative sales growth for 2012 compared to 2011 and has remained negative for the third month in a row.

The model’s previous month’s forecast expectation for August’s actual sales was $24.8 billion as shown in the first table. This forecasted sales number generated last month was much higher than the just published actual August sales of $23.013 billion (larger by $1.76 billion or down 7.1 percent). This results in an M.I. (Momentum Indicator) of minus 7.1 implying that the sales growth trend will be ‘marginally’ down (that is, more negative) over the near term forecast horizon.

Incorporating August’s just published actual sales number into the Cowan LRA forecasting model also produces the latest updated sales and sales growth forecast expectations for the remaining two quarters of 2012 as well as for the four quarters of 2013.

These results are summarized in the first table. Also provided in the table are the corresponding previous month’s sales and sales growth forecast numbers which were determined last month thereby providing sequential monthly forecast estimate comparisons.

As displayed in the table, the latest projected full year 2012 global semi sales forecast estimate decreased to $294.6 billion from last month’s sales forecast expectation of $298.0 billion, a decrease of $3.5 billion or down sequentially by 1.2 percent. Correspondingly, the updated 2012 sales growth forecast expectation declined to minus 1.7 percent from last month’s sales growth forecast estimate of minus 0.5 percent, a decrease of 1.2 percentage points, still remaining in the negative territory; however, more negative than last month.

Virtual prototyping ready for masses

Device volume, variety and complexity are only going to increase. Transformative technologies like virtual prototypes give organizations the tools to transcend challenges. Companies like Altera are creating competitive advantage and innovation with these solutions. Virtual prototyping is now ready for the masses.

Industry trends and challenges make virtual prototyping a must-have solution. New realities make prior adoption barriers mere myths. Virtual prototyping has become a key process for early software development and supply chain enablement. Industry trends also alter design requirements. For instance, earlier, it used to be computing and single core, which has since moved on to connectivity and multi-core.

This opens up implications for SoC development, especially, in terms of increased complexity and volume of software. There is a need to get the architecture right. No amount of downstream tools will compensate for the fundamentally wrong architecture. There is also a need to start software development earlier, in parallel with hardware design. Needless to say, hardware-software integration must be accelerated and system validation will minimize waterfall development process.

New realities of prototyping render prior barriers as mere myths. For instance, earlier, it was believed that creating a prototype is hard. IP models, TLMCentral and model creation software have come a long way, in reality. Earlier, there was a need to wait for complete prototype. Now, software can be developed incrementally and VDKs are jumpstarting the software development. Earlier, one felt the need to change software environment. In reality, the very same tools, debuggers and environment used for hardware can be used here.

Also, today, there are multiple use cases, verticals and customers of virtual prototyping. There is industry support for system-level models. The TLMCentral is an open, web-based portal that provides consolidated access to transaction-level models available across the industry, helping virtual prototype developers accelerate the creation and deployment of their prototypes for early software design.

Open and free, TLMCentral is the first industry-wide portal to aggregate available transaction-level models. It has over 1,000 models of most common IP blocks and interfaces for wireless, consumer and automotive applications. TLMCentral is supported by leading IP vendors, tool providers, service companies and universities. It also offers model developers, architects and software engineers an infrastructure for news, forums and blogs.

Integrated into the software development environment, there are popular debuggers, powerful controls and debugging information. VDK is a great starting point and for ongoing use. One can install and start using. There is no need to wait for months for a prototype. Templates, sample software and reference prototypes are available in one place. Post-silicon support and validation is provided, besides early availability for software development and testing.

Key process for earlier software development includes hardware-software integration and system validation. Semis are engaging customers earlier. The VDKs are driving tangible time-to-volume reduction. Tangible benefits of virtual prototyping include faster time to revenue, faster customer success, and faster field and ecosystem readiness.

MEMS to be $21 billion market by 2017: Yole

The MEMS market is on a growing curve again, and many changes are happening on the technical side, business model side and supply chain side. MEMS will continue to see steady, sustainable double digit growth for the next six years: 13 per cent CAGR in revenues and 20 per cent CAGR in units. MEMS will grow to $21 billion market by 2017.

Every year brings new business to the MEMS landscape. Combo sensors are coming. The MEMS market is still very fragmented, with a number of high volume MEMS applications still limited today. However, a whole range of new MEMS devices has now reached the market and new ‘emerging MEMS’ devices are coming..

MEMS applicable to mobile devices (RF MEMS switches, oscillators, auto-focus) have the possibility to ramp up to large volumes quickly. Growth will also come from existing sensors that are expanding into new market spaces: e.g. pressure sensors for consumer.

Consumer/mobile applications are driving about 50 per cent of the total volume. Telecom and medical applications will grow faster with expected CAGR of ~20 per cent in the next five years. Industrial MEMS applications represent significant opportunities with grow of ~13 per cent likely.

MEMS in 2011
Four devices represented over 50 per cent of units shipped in 2011. Microphones, accelerometers, gyroscopes and magnetometers represented more than 50 per cent of MEMS units shipped in 2011.

Accelerometer, gyroscope and electronic compass growth is coming from the detection of movement, which is reaching every applications, from mobile phones to pacemakers to smart munitions. Microphone has found a sweet spot in the mobile phone business, replacing the electric condenser type of microphones.

All these devices are about to be combined with other sensors and electronic functions/processing in order to add more value. Multi-microphone arrays with noise cancellation functionalities are now a new feature in smartphones. Accelerometers plus gyroscopes plus electronic compasses are being combined (in a SiP package, in the near future, in silicon SoC) to bring a higher level of functionality at even lower costs.

Invensense achieved the same MEMS size when moving from 2-axis to 3-axis gyros (ITG-3200). As for MEMS accelerometer roadmap, new packaging concepts (such as metal-to-metal wafer bonding, WLP/TSV technologies) are driving the ‘Moore law’ of the MEMS technology roadmap.

In an example of STM accelerometer using TSV technology, by removing the area reserved for I/O pads, the TSV process allows the MEMS die area to be shrinked by 25 per cent compared to the standard accelerometer. However, TSV adds major manufacturing changes that increase the final wafer cost by about $90. The wafer extra cost cumulated with a shrinked MEMS die, makes the final die cost still competitive.

In the 2011 MEMS ranking of the top 30 players, TI, STMicro, HP and Bosch are the ‘big 4′ players with annual revenues of > $700 million. The top 30 accounts for ~80 per cent of total MEMS market. More than 25 players generate annual revenues from $50 million to $300 million.

As for 2011 MEMS foundry rankings, some MEMS IDMs have been successful in developing a MEMS foundry business beyond internal needs. STMicro is by far the no. 1 with key customers such as HP (related to ink-jet MEMS manufacturing). Sony has Knowles’ silicon microphone wafer manufacturing business.

Pure play MEMS foundries include Silex (SW), DALSA (CA), apm (TW), IMT (US), tMt (TW) and DNP (JP). CMOS wafer foundries are entering the MEMS manufacturing space with TSMC (TW), umc (TW), Globalfoundries (SG), SMIC (CH), X-Fab (GE) and Semefab (UK).

The 2011 MEMS foundry services accounted for ~6 per cent of the total MEMS market ($623 million). In 2010, the ratio was similar. Now, there are more and more fabless companies in the MEMS space! There are over 70 fabless MEMS companies.

TSMC on 450mm transition: Lithography key!

TSMC unveiled its schedule for 450mm mass production at the recently held SEMICON Taiwan 2012 450mm Supply Chain Forum. Focusing on lithography as the key, Dr. C.S. Yoo, senior director of the 450mm program at TSMC, noted that IC makers and equipment suppliers should fully leverage the G450C. They need to work and innovate to make the 450mm transition a great success.

TSMC has always been in the relentless pursuit of technology innovation. It has been part of all of the computing waves that have driven the market growth. Right now, mobile computing is the leading market driver. TSMC has been helping the industry produce comprehensive, powerful mobile computing devices.

The future growth drivers and trends include mobile computing, cloud computing and smart devices. However, technical and economic challenges also lie ahead. TSMC has been pushing the lithography roadmap. 28nm is said to be the limit of conventional single-patterning lithography. TSMC has innovations to extend immersion to 20nm. The next-generation lithography (NGL) is being preferred beyond 20nm. Also, EUV and multiple-e-beam concept and feasibility has been proven. The more than 10x throughput gap requires collaborative innovation and funding.

TSMC continues to invest in R&D for transistor architecture trends. There is increasing technology complexity, as reflected by mask layers increase. The technology shrink also leads to design complexity.

There are challenges such as intrinsic wafer cost parity and uncertain technology migration ROI. TSMC’s mission is to be the trusted technology and capacity provider for the global logic IC industry for years to come. TSMC already has capacity leadership. TSMC’s total 12″ cleanroom space will equal more than 32 World Cup football fields by the end of this year..

TSMC customers’ expectations include the offer of leading-edge technology, continue to expand capacity, enable faster time to market, faster technology ramp up, faster manufacturing cycle times, and lower cost /die. To bridge the cost and productivity gap, TSMC no longer maintains cost/transistor trend by 2018 due to the slowing pace of technology shrink, and increasing technology complexity.

Cadence Allegro 16.6 Accelerates Timing Closure

Cadence Design Systems Inc. has released the Allegro/OrCAD 16.6 that provides unmatched, scalable design solutions addressing technology challenges.

Allegro is meant for simple to more complex boards, for the geographically dispersed design teams. They also cater to the personal productivity needs for start-ups and small to medium companies. It provides high-speed, power aware SI, HDI managed design environments, that is meant for medium to large enterprises.

Allegro, Sigrity and OrCAD – major themes of Allegro PCB 16.6
The major themes of Allegro PCB 16.6 include the first ECAD collaborative environment for work-in-progress (WiP) PCB design using Microsoft SharePoint. It accelerates the timing closure for high-speed interfaces such as DDRx. There is support for advanced miniaturization techniques that embed passive and active components on inner layers of a PCB.

Regarding the percentage of enhanced miniaturization capabilities for embedding dual-sided and vertical components, Hemant Shah, product marketing director, Allegro PCB and FPGA Products, Cadence, said: “Components with dual-sided contacts offer customers the ability to connect to the components pins through the layer above or through the layer below. This provides routing flexibility. It also allows customers who want redundant connections on inner layers.”

There can be accelerated design implementation through flexible PCB team design capability. Leveraging GPUs for faster display, you can pan and zoom on dense PCBs, enabling greater design productivity.

Typical product creation environment includes the best-in-class hardware design environment for implementation, analysis and compliance sign-off. The design team collaboration capability encompasses design-chain partners. The design data can be integrated into corporate systems to manage cost and quality, and provide visibility. This facilitates on-time release into manufacturing to build products.

Allegro, OrCAD and Sigrity ensure product creation with the best-in-class PCB design environment. Design team collaboration and productivity is integrated at the PCB. Design data integration is also done into corporate systems to manage cost and quality. There is on-time release into manufacturing to build products. Allegro, OrCAD and Sigrity are helping create market leading products.

Users can create the first ECAD collaborative environment using Microsoft SharePoint. Design creation and collaboration trends include geographically distributed teams, increase in outsourcing (OEMs-ODMs), product life cycle management tools are not designed/targeted for managing work-in-progress data. For every design engineer, there are 3X-5X collaborators, reviewers, etc.

The Allegro Design workbench integrates seamlessly to SharePoint 2010. The Team Design Authoring cockpit facilitates design data in and out of SharePoint providing WiP design data management. There is block level check-in, check-out, etc. SharePoint is already deployed in many companies. It is scalable from single server to cloud environment. It has rich platform for power users to configure and developers to customize.

By creating the first ECAD collaborative environment, users can reduce the product creation time by up to 40 per cent. Chances of first pass failure are also reduced from 25 per cent to 1 per cent. Users can accelerate the timing closure on high-speed, multi-Gigabit signals.