Non-mainstream packaging in MEMS, LED and power electronics

The number of MEMS and sensors going into mobile, consumer and gaming applications is expected to continue to skyrocket. As a result, OSAT and Wafer foundry players are getting more and more interest in MEMS module packaging, as volume and complexity of MEMS SiP modules is increasing dramatically, said Dr. Eric Mourier, Yole Developpement.

It implies that IDMs needs to find second source partnersand qualify some OSATs in order to secure their supply chain. Also, standardization(coming from both foundries, OSAT, WLP houses or substrate suppliers) is critical and necessary to implement in order to keep the packaging, assembly, and test cost of MEMS modules under control. There are many different players with different designs, and it’s not likely we’ll see one solution adopted by all the players.

As for wafer-level packaging (WLP) for LEDs, WLP has not been strongly deployed in the LED industry due to associated technical challenges.

In the short-term, there is ESD integration in Si substrate. In the long-term, LED drivers could be integrated at the package level for Intelligent lighting. Ultimately, there are wafer-to-wafer manufacturing schemes for certain packaget types.

Real production of HB-LEDs with a mixed approach of WLP+through silicon vias (TSV) is just starting. There are some Taiwanese players such as TSMC, Xintec, Visera, Touch MicroTech and Sibdi, and South Korea-based LG Innotek. Additional players in the semiconductor and MEMS industry are seeking to enter the field.

SEP 2 IP-based energy management for home

What exactly is smart energy profile (SEP 2) IP-based energy management for the home? Introducing the SEP 2, Tobin Richardson, chairman and CEO, ZigBee Alliance said ZigBee smart energy is the standard of choice for home area networks (HANs).

About 40+ million ZigBee electric meters are being deployed. ZigBee smart energy is being enhanced by network/communications options, support for forward-looking developments, etc. SEP 2 is a joint effort with the HomePlug Alliance. There is a vision of MAC/PHY agnostic SmartEnergy profile.

Robby Simpson, SEP 2 Technical Working Group Chair, system architect, GE Digital Energy, provided the features and benefits of Smart Energy. Features include price communication, demand response and load control, energy usage information/metering data, prepayment metering, text messaging, plug-in electric vehicles, distributed energy resources, billing communication, etc.

Example applications are many, such as smartphones, ESI in the sky, tablets, TVs, plug-in electric vehicles, PCs, solar inverters, thermostats, energy management systems, smart meters, building management systems, smart appliances, etc. There is support for a variety of architectures. The use of IP eases convergence and architecture changes. A consortium for SEP 2 interoperability (CSEP) has been established.

Skip Ashton, ZigBee Arch. review committee chair, senior apps director, Silicon Labs said implementations of SEP 2 are available from a number of companies and across several MAC/PHYs. All standard documents are available for review.

Jeff Gooding, Southern California Edison (SCE), spoke about creating SEP 2 energy ecosysyems. SEP 2 can bridge multi-platform customer technologies to create a rich ecosystem. SEP 2 customer focused solutions can allow the utilities and energy service providers to use any customer communication channel. SEP 2 pilots at SCE include a gateway pilot and a smart charging pilot. Both are separate pilots.

On-chip networks: Future of SoC design

Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.

John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage - saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.

Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.

Incidentally, there are several SoC integration challenges such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.

SGN exceeds requirements
SGN met the tablet performance requirement with fabric frequency of 1066MHz. It has an efficient gate

count of 508K gates. There are features such as an advanced system partitioning, security and I/O coherency. There is support for system concurrency as well as advanced power management.

Sonics offers system IP solutions such as SGN, a router based NoC solution, with flexible partitioning and VC (Virtual Channel) support. The frequency is optimized with credit based flow control.

SSX/SLX is message based crossbar/ShareLink solutions based on interleaved multi-channel technology. It has target based QoS with three arbitration levels. The SonicsExpress is for power centric clock domain crossing. There is sub-system re-use and decoupling.

The MemMax manages and optimizes the DRAM efficiency while maintaining system QoS. There is run-time programmability for all traffic types. The SonicsConnect is a non-blocking peripheral interconnect.

Convergence of PV materials, test and reliability: What really matters?

SEMI, USA recently hosted the seminar on 'Convergence of PV Materials, Test and Reliability: What Really Matters?
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Reliability in growing PV industry
Speaking on the importance of reliability to a growing PV industry - Sarah Kurtz, principal scientist,

Reliability group manager, NREL, said that confidence in long-term performance is a necessity in the PV industry. Current failure rates are low. There is need to demonstrate confidence so that failure rates will stay low. There has been exponential growth of the PV industry so far. PV is a significant fraction of new installations. It now represents a significant fraction of new electricity generating installations of all kinds.

How does one predict the lifetime of PV modules? There has been a qualification test evolution for JPL block buys. Most studies of c-Si modules show module failures are small. Internal electrical current issues often dominate.

The vast majority of installations show very low PV module failure rates (often less than 0.1 percent). There has been evidence that PV is low risk compared to other investments. To sustain the current installation rate, we need to demonstrate confidence that justifies the annual investment of $100 million or so.

Critical factors in economic viability of PV
DuPont has broad capabilities under one roof. It offers materials, solar cell design, and processes integrated with panel engineering. Speaking about critical factors in economic viability of PV - materials matter, Conrad Burke, global marketing director, DuPont PV Solutions, said that material suppliers have a distinct advantage to view trends. The industry can expect consolidation among large PV module producers and large materials suppliers.

There is an increasing dependence on materials suppliers for processes, tech support and roadmap. There is renewed attention to long-term reliability and quality of materials in PV products.

There is a race for survival among panel producers. There are dropping prices for solar panels, and quality is getting compromised. There are reduced incentives in established markets. The market will continue to grow. Key factors that determine investment return for PV include lifetime, efficiency and cost.

When materials fail, the consequences are dire. There are failures such as encapsulant discoloration, backsheet failure, glass delamination, etc. Average defect rates in new-build modules has been increasing. Significant number of PV installations do not deliver the projected RoI. The system lifetime is as important as cost and incentives.

Solar cell power continues to improve. There have been improvements from metal pastes and processes. Performance loss impacts the RoI. The US Department of Energy hired JPL to develop 30-year PV modules. Recent cost pressures have led to the dramatic changes in module materials and a lack of transparency.

Analyzing modules from the recent service environments show performance issues. Certification does not mitigate risk. Tests do not predict the actual field performance. He showed tier-1 solar panel manufacturing problems from China, Japan and the USA. Backsheet is critical to protect solar panels. Few materials have lengthy field experience. We will continue to see drop in prices for solar panels and opening of new markets. Focus for PV module makers will remain efficiency, etc.

Why do we need 450mm wafers?

Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every eighteen months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield - this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation - this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes - this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus, at the 300mm transition, the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.

In addition, larger wafers and better yields allowed larger die sizes, which also reduced the cost of packaging and test, with wafer-scale integration once touted as a solution to reduce costs further at least for large systems. However, in recent years, the average die size has in fact shrunk and it is believed we are now around the optimal die sizes.

As mentioned above, some costs are not inherently reduced by a larger wafer size. Lithography costs are more or less proportional to the total area although small savings are still made as a smaller proportion of time is spent moving onto to the next wafer, whilst tasks such as metrology and CMP also increase somewhat with wafer size.

The result is that the cost of these types of operations grow as a percentage of the total cost of wafer processing and so in a following wafer size transition the savings made are on a smaller percentage of the overall processing cost. Thus, there comes a point where wafer processing costs are dominated by operations not effected by a wafer size increase and so increasing the wafer size becomes uneconomic.

Furthermore, although disputed by some companies, the International Technology Roadmap for Semiconductors (ITRS) has been predicting a slowdown in the rate of the technology cycle defined in Moore’s Law from two years to three years, resulting in a slowing of the increase in functional density per square centimetre.

At the same time the cost of wafer processing is predicted to grow far more rapidly than in the past due to the need to introduce new processes or processing techniques at every node. An interesting slide from ARM below paints a picture of this well. Obviously, it is not the actual new process names in the boxes that count so much as the fact there are so many of them.

Focusing light on breast cancer diagnostics

A team of scientists at the Massachusetts Institute of Technology (MIT), comprising principally of Dr. Ishan Barman, Dr. Narahara Chari Dingari and Dr. Jaqueline Soares, and their clinical collaborators at University Hospitals, Cleveland have developed the Raman scattering-based concomitant diagnosis of breast cancer lesions and related micro-calcifications.

Let’s find out more about this new breast cancer research done by the team at MIT.

Early detection necessary!
According to MIT, one in eight women in the US will suffer from breast cancer in her lifetime and breast cancer is the second leading cause of cancer death in women. Worldwide, breast cancer accounts for 22.9 percent of all cancers (excluding non-melanoma skin cancers) in women. In 2008, breast cancer caused 458,503 deaths worldwide (13.7 percent of cancer deaths in women).

Therefore, technological advancements for its early detection and subsequent treatment can make a significant impact by preventing patient morbidity and mortality and reducing healthcare costs, and are thus of utmost importance to society. Currently, mammography followed by stereotactic breast biopsy serves as the most promising route for screening and early detection of cancer lesions.

Nearly 1.6 million breast biopsies are performed and roughly 250,000 new breast cancers are diagnosed in the US each year. One of the most frequent reasons for breast biopsy is microcalcifications seen on screening mammography, the initial step in early detection of breast cancer. Microcalcifications are micron-scale deposits of calcium minerals in breast tissue that are considered one of the early mammographic signs of breast cancer and are, therefore, a target for stereotactic breast needle biopsy.

However, despite stereotactic guidance, needle biopsy fails to retrieve microcalcifications in one of five breast biopsy patients. In such cases, the resulting breast biopsies are either non-diagnostic or false-negative, thereby, placing the patient at risk and potentially necessitating a repeat biopsy, often as a surgical procedure.

There is an unmet clinical need for a tool to detect microcalcifications in real time and provide feedback to the radiologist during the stereotactic needle biopsy procedure as to whether the microcalcifications seen on mammography will be retrieved or the needle should be re-positioned, without the need to wait for a confirmatory specimen radiograph.

Such a tool could enable more efficient retrieval of microcalcifications, which would, in turn, minimize the number of x-rays and tissue cores required to achieve a diagnostic biopsy, shorten procedure time, reduce patient anxiety, distress and discomfort, prevent complications such as bleeding into the biopsy site seen after multiple biopsy passes and ultimately reduce the morbidity and mortality associated with non-diagnostic and false-negative biopsies and the need for follow up surgical biopsy.

If 200,000 repeat biopsies were avoided, at a cost of $5,000 per biopsy (a conservative estimate and would be much higher for surgical biopsies), a billion dollars per year can be saved by the US healthcare system. The MIT Laser Biomedical Research Center, has recently performed pioneering studies to address this need by proposing, developing and validating Raman and diffuse reflectance spectroscopy as powerful guidance tools, due to their ability to provide exquisite molecular information with minimal perturbation.

Specifics of the technique
Stating the specifics of the technique developed by MIT, the team said that their research focuses on the development of Raman spectroscopy as a clinical tool for the real time diagnosis of breast cancer at the patient bedside. “We report for the first time development of a novel Raman spectroscopy algorithm to simultaneously determine microcalcification status and diagnose the underlying breast lesion, in real time, during stereotactic breast core needle biopsy procedures.”

In this study, Raman spectra were obtained ex vivo from fresh stereotactic breast needle biopsies using a

compact clinical Raman system, modeled and analyzed using support vector machines to develop a single-step, Raman spectroscopy based diagnostic algorithm to distinguish normal breast tissue, fibrocystic change, fibroadenoma and breast cancer, with and without microcalcifications.

The developed decision algorithm exhibits a positive and negative predictive value of 100 percent and 96 percent, respectively, for the diagnosis of breast cancer with or without microcalcifications in the clinical dataset of nearly 50 patients.

Significantly, the majority of breast cancers diagnosed using this Raman algorithm are ductal carcinoma in situ (DCIS), the most common lesion associated with microcalcifications, which has classically presented considerable diagnostic challenges.

This study demonstrates the potential of Raman spectroscopy to provide real-time feedback to radiologists during stereotactic breast needle biopsy procedures, reducing non-diagnostic and false negative biopsies. Indeed, the proposed approach lends itself to facile assembly of a side-viewing probe that could be inserted into the central channel of the biopsy needle for intermittent acquisition of the spectra, which would, in turn, reveal whether or not the tissue to be biopsied contains the targeted microcalcifications.

Coto announces MEMS based magnetically operated switch

According to Stephen Day, VP of Technology, Coto Technology has the number 1 share in reed relays and relay products. The Coto brand is associated with the broadest portfolio, best in class quality, dedicated technical support, and a provider of innovative solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Coto has announced the RedRock, a new MEMS based magnetically operated switch. The RS-A-2515 is the world's smallest wafer level packaged magnetically operated reed switch. It consumes zero power, measures 2mm3 in footprint and switches at less than 0.3W. It delivers high reliability and surface mount package.

The small footprint means use of less PCB real estate, no operate power means a longer battery life. The low switching power leads to higher reliability. The high directionality leads to resistance to stray fields. Hot switchable feature leads to higher reliability.

Together, Coto has managed to combine the best of two worlds -- traditional reed switches with MEMS processing. There is high aspect ratio microfabrication (HARM). This is the first commercially available switch. It produces structures that generate strong contact closure forces. The forces are many times greater than the previous MEMS based magnetic switches. It also enables hot switching up to several hundred milliwatts.

HARM is the key to making it all possible. The benefits are many, from temperature rise vs. carry current, to RedRock contact life test, 1V 1 mA hot-switched load. RedRock allows for small size, zero power consumption and high power switching.

At the moment, Coto is leveraging RedRock into high growth applications. In the future, Coto will integrate sensor solution as well. RedRock's unique combination of features include reed -- no power and high current, and MEMS -- no power and small size, as well as GMR/Hall -- small size and high current -- to deliver the RedRock, which features no power, small size and high current.