Spark’s back on Indian electronics!!

Well, well, well! Post the announcements by the Government of India last week of two 300mm fabs in India, this week, there have been a spate of announcements again! Here's what they are!

Yesterday evening, the Indian Cabinet Committee on Economic Affairs has approved setting up of Information Technology Investment Region (ITIR) near Hyderabad. Phase I will be from 2013 to 2018 and Phase II will be from 2018 to 2038.

The Government of Andhra Pradesh has delineated an area of 202 sq. kms. for the proposed ITIR in three clusters/ agglomerations viz.:

(i) Cyberabad Development Area and its surroundings,
(ii) Hyderabad Airport Development area and Maheshwaram in the south of Hyderabad, and
(iii) Uppal and Pocharam areas in eastern Hyderabad. The ITIR will be implemented in two phases.

Next, the Government of India finalized the setting up of a ‘Ultra-Mega Green Solar Power Project' in Rajasthan in the SSL (Sambhar Salts Ltd, a subsidiary of Hindustan Salts Ltd - a Central Public Sector Enterprise under the Department of Heavy Industry, Ministry of Heavy Industries & Public Enterprises) area close to Sambhar Lake, about 75 kms from Jaipur.

Further, India was recognized as ‘Authorizing Nation' under the international Common Criteria Recognition Arrangement (CCRA) to test and certify electronics and IT products with respect to cyber security. India has become the 17th nation to earn this recognition.

Then again, the ‘HTML 5.0 Tour in India' has now reached Hyderabad.

Also, India has offered to help Cuba develop its renewable energy resources. This has been conveyed to Marino Murillo, vice president of the Republic of Cuba at Havana, by Dr. Farooq Abdullah, Minister of New and Renewable Energy, during his trip to Cuba.

All of this is really brilliant stuff!

At least, I have never seen or heard about so much activity happening, especially in the electronics and solar PV sectors. One sincerely hopes that all of these initiatives will allow India to come to the forefront of the global electronics industry.

The spark seems to be coming back to the India electronics industry, after a very, very long wait! It is hoped that this stays on!!

ST intros STM32F4 series high-performance Cortex-M4 MCUs

STMicroelectronics has introduced the STM32F4 series STM32 F4x9 and STM32F401, which are high-performance Cortex-M4 MCUs.

On the growth drivers for GP MCUs, the market growth is driven by faster migration to 32 bit platform. ST has been the first to bring the ARM Cortex based solution, and now targets leadership position on 32bit MCUs. An overview of the STM32 portfolio indicates high-performance MCUs with DSP and FPU up to 608 CoreMark and up to180 MHz/225 DMIPS.

Features of the STM32F4 product lines, specifically, the STM32F429/439, include 180 MHz, 1 to 2-MB Flash and 256-KB SRAM. The low end STM32F401 has features such as 84 MHz, 128-KB to 256-KB Flash and 64-KB SRAM.

The STM32F401 provides the best balance in performance, power consumption, integration and cost. The STM32F429/439 is providing more resources, more performance and more features. There is close pin-to-pin and software compatibility within the STM32F4 series and STM32 platform.

The STM32 F429-F439 high-performance MCUs with DSP and FPU are:

• World’s highest performance Cortex-M MCU executing from Embedded Flash, Cortex-M4 core with FPU up to 180 MHz/225 DMIPS.
• High integration thanks to ST 90nm process (same platform as F2 serie): up to 2MB Flash/256kB SRAM.
• Advanced connectivity USB OTG, Ethernet, CAN, SDRAM interface, LCD TFT controller.
• Power efficiency, thanks to ST90nm process and voltage scaling.

In terms of providing more performance, the STM32F4, they provide up to 180 MHz/225 DMIPS with ART Accelerator, up to 608 CoreMark result, and ARM Cortex-M4 with floating-point unit (FPU).

The STM32F427/429 highlights include:
• 180 MHz/225 DMIPS.
• Dual bank Flash (in both 1-MB and 2-MB), 256kB SRAM.
• SDRAM Interface (up to 32-bit).
• LCD-TFT controller supporting up to SVGA (800x600).
• Better graphic with ST Chrom-ART Accelerator:
-- x2 more performance vs. CPU alone
-- Offloads the CPU for graphical data generation
* Raw data copy
* Pixel format conversion
* Image blending (image mixing with some transparency).
• 100 μA typ. in Stop mode.

Some real-life examples of the STM32F4 include the smart watch, where it is the main application controller or sensor hub, the smartphone, tablets and monitors, where it is the sensor hub for MEMS and optical touch, and the industrial/home automation panel, where it is the main application controller. These can also be used in Wi-Fi modules for the Internet of Things (IoT), such as appliances, door cameras, home thermostats, etc.

These offer outstanding dynamic power consumption thanks to ST 90nm process, as well as low leakage current made possible by advanced design technics and architecture (voltage scaling).

ST is making a large offering of evaluation boards and Discovery kits. The STM32F4 is also offering new firmware libraries. SEGGER and ST signed an agreement around the emWin graphical stack. The solution is called STemWin.

Great, India’s having fabs! But, is the tech choice right?

The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:

Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.

Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.

Now, this is excellent news for everyone interested in the Indian semiconductor industry.

One look at the numbers above tell me - NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let's examine!

As you can probably see, both the projects have placed 22nm right at the very last phase! That's very interesting!

Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel's Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!

For discussion's sake, let's say, a fab in India comes up by say, early 2015. Let's assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn't it? Where will the rest of the global industry be by then?

You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members.

What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE's Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY's College of Nanoscale Science and Engineering!

So, what does all of this tell me?

One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space!  Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!

Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop right there!

Perhaps, these product lines will be good for India and serve well, for now, but not for long!

Now, India to have two semicon fabs!

Finally, the Government of India has approved the establishment of a semiconductor wafer fab (fab) in India!

This is indeed heart warming news, especially for the Indian semiconductor and electronics industries. For years, India has been trying to get at least one fab up and running! Now, the dream is about to be realized!

Speaking from China, an ecstatic BV Naidu, chairman and managing director, Sagitaur Ventures, co-chairman, Karnataka ICT Grioup and former president, India Semiconductor Association (ISA) said: “This is really a fantastic news for the Indian semiconductor industry. The government has been trying to achieve this since 2008. The announcement goes as a strong signal to global community.”

Pradip Dutta, corporate VP and MD, Synopsys, said: “It is a momentous decision for the semiconductor industry and by extension the electronics industry for our country. It should lead to a level playing field for the local manufacturers and mitigate some of the disability factors. I sincerely hope the industry reacts positively to this news and this leads to a vibrant local IC design industry.”

Raghu Panicker, sales director, Mentor Graphics India, added: “For years, India has been trying to get at least one fab up and running! This has indeed been a long awaited news. Finally its not ONE, but TWO. The fabs would fuel the growth of semicon start up’s and electronics industry as a whole. It is a big step forward for the overall ESDM inititaive by IESA and government.”

Jaypee Group, IBM and Tower form one consortium. HSMC, STMicroelectronics and a Malaysian company are said to be part of the other consortium.

Higher levels of abstraction growth area for EDA

San Jose, USA-based Atrenta's SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.


I started by asking how Atrenta provides early design analysis for logic designers? He said: "The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate 'predictions', without the time and cost required to actually send a design through detailed implementation."

There's a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.

Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.

How are SpyGlass and GenSys platforms helping the semiconductor industry? Dr. Ajoy Bose said: "SpyGlass is Atrenta’s platform for RTL Signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams. 

"GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done."

How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.

On another note, I asked him why Apple's choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.

Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: "We see strong growth.  Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry.  At a macro level, the consumer sector will drive a lot of the growth ahead.  For EDA, the higher levels of abstraction is where the growth will be."