Accelerating EDA innovation through SoC design methodology convergence

According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.

A design engineer's project time for doing design has reduced by 15 percent from 2007-2014, while the engineer's time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!

Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.

The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.

Macro trends
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.

There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.

The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.

The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.

Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.

The goal of system-level checking is performance, power analysis and  SoC functionality. Also, there are SoC 'features' that need to be verified.

A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!

The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.

SEMICON Europa 2014 calls for innovators

SEMICON Europa 2014 will be held at Grenoble, France, on October 7-9 October, 2014. The event will see over 400 exhibitors, which means, the exhibition area has expanded by over 40 percent vs. 2013. There will be over 70 programs featuring 300+ speakers. SEMI expects 6,000+ visitors.

A feature of the event will be the Innovation Village that will feature 35 start-ups. I have been just informed that four start-ups have cancelled. So, that leaves 31 start-ups: ActLight, Aryballe, Avalun, Bluwireless Technology, CALAO Systems, Enerstone, Euresis, Epigan, Evaderis, Exagan, Feeligreen, Genes'Ink, Grapheat, Gridbee, Heyday, Hotblock Onboard, Imagsa Technology, Irlynx, Madci, Metablue Solution, Nessos, Nocilis Materials, Noivion, PETsys Electronics, Pollen Technology, Scint-X, Sepcell, Silicon Line GmbH, Smoltek, Sol Voltaics and Wavelens.

A few start-ups are given below:

ActLight SA: It focuses in the field of CMOS photonics.

AVALUN SAS: It currently develops the LabPad®, a next - generation mobile point-of-care (POC) device.

CALAO Systems: It is the specialist of onboard connected computers.

eVaderis: It offers energy efficient, low power mixed - signal data - centric control processors.

Enerstone: It works with rechargeable battery manufacturers and integrators to improve the charge quality of their batteries.

Exagan: It is a leading supplier of Gallium Nitride based transistor devices.

Feeligreen: It provides micro - current devices for dermo - cosmetics and dermo - therapeutics.

Grapheat: It is a young startup specialized in the production and integration of monolayer high - quality of graphene on wafers and substrates for specific applications.

Gridbee Communications: It is developing Innovative long range Mesh Network solution for connected objects.

Heyday: It develops semiconductor ICs for the power conversion market.

Irlynx: It develops and commercializes infrared sensors.

Nessos Information Technologies SA: Nessos is a highly qualified software development company.

Nocilis Materials: It offers various silicon based semiconductor materials.

Noivion: It developed and patented a new thin film deposition technique named Ionized Jet Deposition (IJD).

PETsys Electronics SA: It developed new PET detectors for next generation of medical PET scanners.

Pollen Technology: It is a software company.

Scint-X: It develops and produces cutting - edge structured scintillators.

Silicon Line: A leading global provider of innovative ultra - low power optical link technology for mobile and consumer electronics markets.

Smoltek AB: It offers a proprietary conductive nano - scale carbon technology.

Wavelens: It is developing disruptive optical MEMS solutions.

On October 7, there will be a five-minute pitch for each start-up participating. It will be followed by a panel discussion: 'Fundraising for the Future Champions of European Electronics: Strategies, Challenges and Opportunities. Day two will host the Innovation conference.

DVCon India 2014 aims to bring Indian design, verification and ESL community closer!

DVCon India 2014 has come to Bangalore, India, for the first time. It will be held at the Hotel Park Plaza in Bangalore, on Sept. 25-26. Dr. Wally Rhines, CEO, Mentor Graphics will open the proceedings with his keynote. 

Other keynotes will be from Dr. Mahesh Mehendale, MCU chief technologist, TI, Janick Bergeron, verification fellow, Synopsys, and Vishwas Vaidya, assistant GM, Electronics, Tata Motors.

Gaurav Jalan, SmartPlay, chair – promotions committee took time to speak about DVCon 2014 India.

Focus of DVCon 2014 India
First, what's the focus of DVCon 2014 India? According to Jalan, DVCon has been a premiere conference in the US contributing to quality tutorials, papers and an excellent platform for networking. DVCON India focuses on filling the void of a vendor neutral quality conference in the neighbourhood - one that will grow over time.

The idea is to bring together, hitherto dispersed, yet substantial, design, verification and ESL community and give them a voice. Engineers get a chance to learn solutions to the verification problems, share the effectiveness of  the solutions they have experimented, understand off the shelf solutions that are available in market and meet the vendor agnostic user fraternity. Moving forward the expectation is to get the users involved as early adopters of upcoming standards and actively contribute to them.

Trends in design
Next, what are the trends today in design? Jalan said while the designs continue to parade on the lines of Moore’s law there is a lot happening beyond the mere gate count. Defining and developing IPs with a wide configuration options serving a variety of application domains is a challenge.

The SoCs are crossing multi billion gate design (A8 in iPhone6 is 2 billion) with multi-fold increase in complexity due to multiple clock domains, multiple power domains, multiple voltage domains while delivering required performance in different application modes with sleek foot print.

Trends in verification
Now, let's examine the trends today in verification. When design increases linearly, verification jumps exponentially. While UVM has settled dust to some extent on the IP verification level, there is a huge of challenges still awaiting to be addressed. The IP itself is growing in size limiting the simulator and encouraging users to move to emulators. While UVM solved the methodology war the VIPs available are still not simulator agnostic and expecting a emulator agnostic VIP portfolio is still a distant dream.

SoC verification is still a challenge not just due to the sheer size but because porting an env from block to SoC is difficult. The test plan definition and development for SoC level itself is a challenge. Portable stimulus group from Accellera is addressing this. Similarly, coverage collection from different tools is difficult to merge. Unified coverage group at Accellera is addressing this. Low power today is a norm and verifying a power aware design is quite challenging. UPF is an attempt to standardize this.

Porting a SoC to emulator to enable hardware acceleration so as to run usecases is another trend picking up. Teams now are able to boot android on an SoC even before the silicon arrives. With growing analog content on chip the onus is on the verification engineers to ensure the digital and analog sides of the chip work in conjunction as per specs. Formal apps have picked so as to address connectivity tests, register spec testing, low power static checks and many more.

Accelearating EDA innovation
So, how will EDA innovation get accelerated? According to Jalan, the semiconductor industry has always witnessed that startups and smaller companies lead the innovation. Given the plethora of challenges around, there are multiple opportunities to be addressed from both the biggies and the start-ups.

The evolution of standards at Accellera definitely is a great step so as to bring the focus on real innovation in the tools while providing a platform for the user community to come forward sharing the challenges and proposing alternates. With a standard baseline that is defined with collaboration from all partners of the ecosystem, the EDA companies can focus on competing on performance, user interface, increased tool capacity and enabling faster time to market.

Forums like DVCON India help in growing awareness on standard promoted by Accellera while encouraging participants from different organizations and geographies join to contribute. Apart from tools areas where EDA innovation would pick up include new IT technologies and platforms – Cloud, Mobile devices.

Next level of verification productivity
Where is the next level of verification productivity likely to come from? To this, Jalan replied that productivity in the verification improves from different aspects. While faster tools with increased capacity comes from innovation at EDA end, standard have played an excellent role in addressing it. UVM has helped in displacing vendor specific technologies to improve inter-operability, quick ramp up for engineers and reusability. Similarly on power format, UPF has played an important role in bridging the gaps.

Unified coverage is another aspect where it will help in closing early with coverage driven verification. IPXACT and SystemRDL standards help further in packaging IPs and easier hand off to enable reuse. Similarly other standards on ESL, AMS etc help in closing the loop holes that prevent productivity.

New, portable stimulus specification now being developed under Accellera that will help in easing out test development at different levels from IP to sub system to SoC. For faster simulations, the increase in adoption of hardware acceleration platforms is helping verification engineers to improve regression turn around time.

Formal technologies play an important role in providing a mathematical proofs to common verification challenges at an accelerated pace in comparison to simulation. Finally events like DVCON enables users to share their experiences and knowledge encouraging others to try out solutions instead of struggling with the process of discovering or inventing one.

More Indian start-ups
Finally, do the organizers expect to see more Indian start-ups post this event? Yes, says Jalan. "We even have a special incubation booth that is encouraging young startups to come forth and exhibit at a reduced cost (only $300). We are creating a platform and soon we will see new players in all areas of Semiconductor.

"Also, the Indian government's push in the semiconductor space will give new startups further incentive to mushroom. These conferences help entrepreneurs to talk to everyone in the community about problems, vet potential solutions and seek blessings from gurus."

Apple continues to 'wow' all over again!

Apple has done it again! Trust the Cupertino-based company to come up with great products -- time after time, after time!

Today, the iPhone 6 and iPhone 6 Plus have been announced! These were followed quickly by announcements regarding the Apple Watch and Apple Pay.

The phones have 4.7-inch and 5.5-inch Retina HD displays, and packed with innovative technologies in an all-new dramatically thin and seamless design. Also, they are engineered to be the thinnest ever. Both models run on the all-new A8 chip and include iOS 8, the very latest version!

The Apple Pay now allows a very easy way to securely pay for physical goods and services in stores or apps with the touch of a finger. You can pay securely and conveniently in stores by holding the phone near the contactless reader and keeping a finger on Touch ID. There is absolutely no need to unlock your iPhone or launch an app!

The Apple Watch introduces a specially designed and engineered Digital Crown that provides an innovative way to scroll, zoom and navigate. It is Apple’s most revolutionary navigation tool since the iPod Click Wheel and iPhone Multi-Touch.

Analysys Mason believes that smartwatches will become the dominant wearable smart device by sales in early 2017, and that, Apple will drive this market. Analysys Mason also feels that Apple has an advantage in the race for mobile commerce and payments dominance.

IHS reports that Apple rarely invents new markets, despite its reputation. But when Apple launches a new product category, it attempts to redefine the market. Apple Pay may also get introduced internationally as soon as possible.

All of my blogs are now up for sale! ;)

My dear friends, as most of you are probably aware, Webstatsdomain.org has estimated Pradeep's Point! at a whopping $19.1 billion in July 2014. As I write this post, the number has slightly reduced to $16.6 billion. Pradeep's Point! is my flagship blog! ;) 

Friends, I am now in the process of selling off Pradeep's Point! as well as all of my other blogs! I hope that they will all remain, as will the content, but the owner (or owners) will be different! Perhaps, the blogs could have a different name!

Maybe, the new owners will try and keep me on board, too! ;) (I hope, they do).

It's been a long time! I started Pradeep's Point! back in 2007, having just returned after my second stint in Hong Kong and China. Actually, it was initially under Blogspot as Pradeep Chakraborty's Blog - when it won the first international award - Pradeep Chakraborty's Blog was selected as the best in the world in the Electronic Hardware category for 2008-10, by Electronics Weekly, UK. I remember and would again like to thank all of those folks who voted for me to the first ever international title! :)

Next, Pradeep Chakraborty's Blog received an Honorable Mention @ Blognet Awards 2009! That's also the time when someone succeeded in adding malware to that blog, and there was absolutely no fault of mine, and it was later removed by Google! I recall spending an entire night migrating the content to Wordpress, where I had a secondary blog - Pradeep's Point!

I moved on to Wordpress, migrated all of the posts, and Pradeep's Point! was reborn, or rather, born!

Thereafter, it has been hugely satisfying journey for me! I managed to pick up at least one international award / international recognition for all of my blogs, every year, till this year! ;) These are:

* PC’s Semicon Blog awarded the Top Digital Media Blog by Online IT Degree (in November 2010).

* Green Gadget of Texas, USA, awarded Pradeep's Point! as the “Featured Tech Site” for 2011!

* In 2012, Gorkana, UK, selected Pradeep's Point! as the Blog Influencer 2012!

* PC's Telecom Blog listed among Best VoIP blogs by HostedSwitch, USA.

* In Feb. 2013, PC's Electronic Components Blog selected as 100 Top Resources for Electrical Engineers on ElectricalEngineeringSchools.org, USA.

* In August 2014, PC's Electronic Components Blog was ranked 11th in the "Top 101 Best Resources for Electrical Engineers.”

Now, this year, the huge estimation of Pradeep's Point! by Webstatsdomain.org!

As I write, two folks - from Bangalore -- are trying to gather funds to buy Pradeep's Point! Although, my personal preference is for a very good friend! :)

The other five blogs up for sale are:
* PC's Semiconductors Blog. (Won an award)
* PC's Solar Photovoltaics Blog.
* PC's Electronics Blog.
* PC's Electronic Components Blog. (Won two awards)
* PC's Telecom Blog. (Won an award)

I already have feelers, again from Bangalore, for buying out PC's Semiconductors Blog and PC's Electronic Components Blog. Again, I would prefer, if a friend, hopefully, tried to buy all of them, together! One blog definitely can't do without the other - that's my estimation! ;) Well, let's see what happens!

So, my dear friends, once again, it has been a pleasure serving you all via my blogs! Now, they are in the process of being sold off. Whoever buys those, will definitely have a great future! :) (In case, I change my mind, the blogs will remain as they are! ;) )

About time ;) I guess!! Thanks everyone, for your tremendous love and continuous support! :)

"I'd rather attempt to do something great and fail, than to attempt to do nothing and succeed!" -- Robert H. Schuller. Yep, I definitely agree!

Cadence now realizing EDA 360 vision: Nimish Modi

The EDA 360 was an industry vision. It reflected a change in market requirements. It was application driven system design. From a Cadence perspective, the company has done system design enablement, according to Nimish Modi, senior VP, marketing and business development, Cadence Design Systems Inc.

In Apple's case, the iOS is unique. Cadence feels that the heart of the design is the SoC. The electrical analysis is becoming very important. For instance, how do you optimize before tape-out? Hardware and software conversion presents a huge problem as well. The IP plays an important part. Cadence did IP-as-a-service. It now has an IP strategy.

Today, EDA is about possibility, not productivity. Cadence provides tools and content for semiconductor and systems companies. It is now realizing the EDA 360 vision.

On IP
According to Modi, each IP is immensely complex. Standards based or interface IP is not enough! Silicon-proven design is the need of the hour. Now, more and more IP blocks are said to be coming together.

FPGA-based prototyping
Cadence is offering the Palladium XP, and its primary use is for system verification. Software development is becoming a little bit difficult. People are providing software prototypes. The Palladium compile, turnaround and debug are very fast, best-in-class. All memory, clocking, partitioning, etc., is now automated.

The capacity of the Protium platform is 100 million gates. It will enable hardware and software developers. The use model for Protium is:
* Hardware folks use it for hardware regression.
* Software folks use it for early software development.

The main value proposition is the faster bring-up time. Also, the Palladium hybrid model helps customers overcome the boot problem. It is a hybrid of emulation and virtual prototyping. The dynamic power analysis is another issue. The Palladium hybrid model helps to do the testing.

Collaboration with ARMARM provides processor IPs. Cadence works closely with ARM. Cadence is also co-optimizing its tools to provide the best PPA. Physical libraries and tools get optimized. Cadence's tools are optimized for ARM architecture. Cadence is also the first ones on the access to the V8 ARM models.

Need for efficient product development ecosystem: CDNLive 2014

According to Vasudevan Aghoramoorthy, VP at Wipro Technologies, a product-centric approach targets multiple customers as well as diverse needs.An example is the desktop server. He was delivering the guest keynote on day two at the CDNLive 2014 in Bangalore, India.

For an app-centric approach, it addresses one specific market and has multiple end customers.Examples are set-top boxes and mobile phones. A services-centric approach addresses the service providers' needs. Examples would be PoS machines, base stations, ATMs, patient monitors, etc.

A customer-centric approach has diverse needs. These are faster time-to-market, diversification into complementary markets, reduction in product costs, completion of product portfolio, market development, expansion and customization, as well as leveraging analytics.

As a case study, he referred to Wipro engineering a low-cost, low-power ATM with battery back-up. It has been implemented with multi-language display and voice instruction, with spoil-proof keyboard. It also has a fingerprint biometric reader, and serves as a tamper-proof machine for secured transactions.

What did the product development process achieve? Product cost was reduced by 60 percent, and power consumption was reduced by 50 percent. The concept to deployment time was 10 months. An innovative design was used to address the strict power requirements. Wipro used an agile approach to develop the product.

Another case was of a patient-monitoring machine at a fraction of the cost. There was cost reduction by 5X at the physician's end and 50 percent at the patient's end. There was ease of use for physicians as connectivity options were enabled for smartphones and tablets.

All of these cases tell us that the product development ecosystem must be efficient. Product management and understanding use cases are key. In Wipro's  case, the development methodology was adapted to market needs. Product differentiation can be done by software. There is a need for cross-disciplinary engineering skills. It will lead to newer methodologies, enabling joint reviews in collaboration for cross-disciplinary projects.

Market opportunities are available for product development and retaining value. Market-driven needs drive innovation, and possibly, lead to the growth of the ESDM sector in India.

Diverse requirements for IoT evolving: Charlie Huang

According to Charlie Huang, senior VP, Worldwide Field Operations and System & Verification Group, Cadence, today, we are talking about tremendous data growth. Mobile has been driving the growth of semiconductors, besides medical, industrial, consumer and automotive electronics as well.

Trends are also driving disruptive opportunities -- from driving growth in China to growth in India. He was delivering the keynote on day two at the CDNLive 2014 in Bangalore, India.

"We can innovate to build things that are yet to be imagined. Greater things are yet to come for the Indian semicon design opportunities.

"Today, the iPad has become a system of systems. Now, everyone is waiting for the next big thing. People are also talking about the IoT. Everything will get revolutionized by the newer SoCs. Diverse requirements for IoT have been evolving. There are development challenges from all directions. More functions also means that more IP cores need to be integrated and verified. The IP cores per SoC is likely to be 123 in 14nm, from 108 in 20/22nm. The complexity is just unimaginable!

"Eighty percent of SoC development costs come from software, verification and validation. We should now look at innovating software design with SoC design.

Cadence has invested substantially in IP. It enables system design enablement from end product down to chip level. System-level design with high level synthesis is used to shorten the development cycle and get better quality of results (QoR).

IoT gathering pace as revolution: Guru Ganesan

By 2020, there will be over 8 billion people on our planet. This will also bring tremendous innovations and challenges. ARM has been connecting intelligence at every level, said Guru Ganesan, president and MD, ARM India.

He was delivering the guest keynote at the recently held CDNLive 2014 event in Bangalore, India.

Newer apps are helping connect with the world. As per Gartner, $27 billion worth apps were downloaded in 2013. By 2020, this is estimated to rise to $80 billion.

According to Ganesan, consumer trends are driving innovation in embedded apps, including rich user interface (UI). ARM is also at the heart of wearable technologies, for example, Smart Glasses from Google. Some examples from India include Lechal from Ducere Technologies, GOQ Pi remote fitness companion, Fin+ navigation and device control gesture based device from RHLVision, and Smarty Ring that brings instant smartphone alerts to your fingers from Chennai.

So, what are the key requirements for wearables? These are video/image, audio, display, software, OS, connectivity and battery life! In 2013, over 1 billion smartphones were shipped. Further, mobile data should grow 12 times over between now and 2018.

In medical electronics, besides humans, it has extended to keeping the cattle healthy and have intelligent agriculture with OnFarm, by using sensors. IoT as a revolution is gathering pace. As per a survey conducted by ARM, 95 percent of the users expect to be using IoT over the next three years. Common standards are being developed for interoperability. Similarly, mobility and connectivity are also happening in automotives.

Now, let's see the development challenges for high-end embedded. Embedded applications today integrate more functions. Consequently, design and verification challenges continue to grow. Further, lot of smart devices are now generating lot of data. The question is: how are we using that data?

Ganesan added that by 2020, there will be new challenges in transportation, healthcare, energy and education. Once devices start communicating with each other, we are likely to see the evolution of a smart infrastructure.

Innovating in system of systems: Lip Bu-Tan

There have been innovations of innovations happening in the global technology industry. IoT, mobility, cloud computing, etc., are creating opportunities for the system of systems, according to Lip-Bu Tan, president and CEO, Cadence Design Systems Inc. He was delivering the main keynote. at the recently held CDNLive 2014 in Bangalore, India,

Some of the trends driving semiconductor growth in end markets include automotives at $24 billion, computers at $76 billion, industrial electronics at $14,1 billion, medical electronics at $12.5 billion, and mobile phones at $100 billion. In India, especially, lot of fabless companies are said to be coming up.

The tablet is a system of systems. It has communications, navigation, recording and photography, etc. Even the automotive vehicle is a convincing example. Next, there is the IoT. There are said to be diverse needs for the IoT.

There are said to be several challenges for the system of systems. Some of these are more IP and software requirements, and more needs for low power and mixed signal. System design enablement requires system integration, packaging and board, etc.

Cadence has a comprehensive SoC IP solution. The mixed signal verification solution ensures functionality, reliability and performance. Cadence also introduced the Voltus-Fi custom power integrity solution in Shanghai the week before. Its Quantus QRC extraction solution gives up to 5X performance.

Next, the Jasper acquisition expands the Cadence development suite. Cadence also provides the FPGA-based prototyping with Palladium flow for software development.

Tan concluded that new technologies always require closer collaboration -- from IP through manufacturing. Cadence is here to help designers innovate -- from systems to silicon.

Cadence Quantus solution meets 16nm FinFET challenges

Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET.

What's the uniqueness about the Cadence Quantus QRC Extraction solution?  KT Moore, senior group director – Product Marketing, Digital and Signoff Group, Cadence Design Systems, said: "There are several parasitic challenges that are associated with advanced node designs — especially FinFET – and it’s not just about tighter geometries and new design rules. We can bucket these challenges into two main categories: increasing complexity and modeling challenges.

"The number of process corners is exploding, and for FinFET devices specifically, there is an explosion in the parasitic coupling capacitances and resistances. This increases the design complexity and sizes. The netlist is getting bigger and bigger, and as a result, there is an increase in extraction runtimes for SoC designs and post-layout simulation and characterization runtimes for custom/analog designs.

"Our customers consistently tell us that, for advanced nodes, and especially for FinFET designs, while their extraction runtimes and time-to-signoff is increasing, their actual time-to-market is shrinking and putting an enormous amount of pressure on designers to deliver on-time tapeout. In order to address these market pressures, we have employed the massively parallel technology that was first introduced in our Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution to our next-generation extraction tool, Quantus QRC Extraction Solution.

"Quantus QRC Extraction Solution enables us to deliver up to 5X better performance than competing solutions and allows scalability of up to 100s of CPUs and machines."

Support for FinFET features
How is Quantus providing significant enhancements to support FinFET features?

Parasitic extraction is at the forefront with the introduction of any new technology node. For FinFET designs, it’s a bit more challenging due to the introduction of non-planar FinFET devices. There are more layers to be handled, more RC effects that need to be modeled and an introduction of local interconnects. There are also secondary and third order manufacturing effects that need to modeled, and all these new features have to be modeled with precise accuracy.

Performance and turnaround times are absolutely important, but if you can’t provide accuracy for these devices — especially in correlation to the foundry golden data — designers would have to over-margin their designs and leave performance on the table.

Best-in-class accuracy
How can Cadence claim that it has the 'tightest correlation to foundry golden data at TSMC vs. competing solutions'? And, why 16nm only?

According to Moore, the foundry partner, TSMC, asserts that Quantus QRC Extraction Solution provides best-in-class accuracy, which was referenced in the recent press announcement:

“Cadence Quantus QRC Extraction Solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.”

FinFET structures present unique challenges since they are non-planar devices as opposed to its CMOS predecessor, which is a planar device. We partnered with TSMC from the very beginning to address the modeling challenges, and we’ve seen many complex shapes and structures over the year that we’ve modeled accurately.

"We’re not surprised that TSMC has recognized our best-in-class accuracy because we’re the leader in providing extraction solutions for RF designs. Cadence Quantus QRC Extraction Solution has been certified for TSMC 16nm FinFET, however, it’s important to note that we’ve been certified for all other technology nodes and our QRC techfiles are available to our customers from TSMC today."

India needs to learn from Intersolar North America show!

Intersolar North America successfully concluded its seventh annual show in the heart of the United States’ largest solar market, California. More than 17,000 visitors from 74 countries visited 530 exhibitors.

The show had the latest innovations in the photovoltaic, energy storage, balance of systems, mounting and tracking systems, and solar heating and cooling market sectors.

It just shows how the USA has evolved as a leading market for solar PV over the years. One could feel USA creeping up on China! Which brings me to the other significant news.

Recently, there was news regarding the USA-China solar dispute. USA has won huge anti-dumping tariffs in the US-China solar panel trade case. A preliminary decision by the US Department of Commerce has imposed significant tariffs on Chinese solar modules in the anti-dumping portion of the case.

The decision has also closed SolarWorld's "loophole," which is said to have allowed Chinese module manufacturers to use Taiwanese cells in their modules, circumventing US trade duties.

Will this affect the Chinese PV module suppliers? Perhaps, not that much. Why so? China itself has a very huge domestic market for solar PV. They can continue to do well in China itself. It can also sell solar PV modules in India, as well, besides other regions in the Asia Pacific.

That brings me back to Intersolar North America 2014. Why was there such a low presence of Indian companies? The exhibitor list for the show reads only two -- Lanco Solar Pvt Ltd and Vikram Solar Pvt Ltd. Where are the others?

If one looks at the Ministry for New and Renewable Energy (MNRE) website, there is a notification stating that a National Solar Mission (NSM) is being implemented to give a boost to solar power generation in the country. It has a long-term goal of adding 20,000 MWp of grid-connected solar power by 2022, to be achieved in three phases (first phase up to 2012-13, second phase from 2013 to 2017 and the third phase from 2017 to 2022).

Well, the MNRE has also put up a release stating complaints received about the non-function of the systems installed by channel partners. Without getting into details, why can't Indian suppliers get to the ground and work up solidly? Some of the complaints are actually not even so serious. System not working. Channel partner not attending complaint! And, plant not working due to inverter (PPS) burnt down. These should be attended to quickly, unless, there is some monetary or other issue, which, at least, I am not aware of!

The CNA Corp.s Energy, Water, & Climate division released two studies earlier this week, which found that cost-effective options that power plants can use to cut water use can also help plants reduce CO2 emissions.

The first report, Capturing Synergies Between Water Conservation and Carbon Dioxide Emissions in the Power Sector, focuses on strategy recommendations based on analyses of water use and CO2 emissions in four case studies, which are detailed in the second report, A Clash of Competing Necessities: Water Adequacy and Electric Reliability in China, India, France, and Texas.

CNA's Energy, Water, & Climate division released two studies, which found that cost-effective options that power plants can use to cut water use can also help plants reduce CO2 emissions.

“It’s a very important issue,” said lead study author Paul Faeth, director of Energy, Water, & Climate at CNA. "Water used to cool power plants is the largest source of water withdrawals in the United States and France, and a large source in China and India.”

“The recommendations in these reports can serve as a starting point for leaders in these countries, and for leaders around the world, to take the steps needed to ensure the reliability of current generating plants and begin planning for how to meet future demands for electric power.”

India needs to learn from the Intersolar North America show. It also needs to look carefully at CNA's reports. It is always great and good work that attracts global attention. India has all of the requred capabilities to do so!

SEMI materials outlook: Semicon West 2014

At Semicon West 2014, Daniel P. Tracy, senior director, Industry Research and Statistics, SEMI, presented on SEMI Materials Outlook. He estimated that semiconductor materials will see unit growth of 6 percent or more. There may be low revenue growth in a large number of segments due to the pricing pressures and change in material.

For semiconductor eequipment, he estimated ~20 percent growth this year, following two years of spending decline. It is currently estimated at ~11 percent spending growth in 2015.

Overall, the year to date estimate is positive growth vs. same period 2013, for units and materials shipments, and for equipment billings.

For equipment outlook, it is pointing to ~18 percent growth in equipment for 2014. Total equipment orders are up ~17 percent year-to-date.

For wafer fab materials outlook, the silicon area monthly shipments are at an all-time high for the moment. Lithography process chemicals saw -7 percent sales decline in 2013. The 2014 outlook is downward pressure on ASPs for some chemicals. 193nm resists are approaching $600 million. ARC has been growing 5-7 percent, respectively.

For packaging materials, the Flip Chip growth drivers are a flip chip growth of ~25 percent from 2012 to 2017 in units. There are trends toward copper pillar and micro bumps for TSV. Future flip chip growth in wireless products are driven by form factor and performance. BB and AP processors are also moving to flip chip.

There has been growth in WLP shipments. Major applications for WLP are driven by mobile products such as smartphones and tablets. It should grow at a CAGR of ~11 percent in units (2012-2017).

Solder balls were $280 million market in 2013. Shipments of lead-free solder balls continues to increase. Underfillls were $208 million in 2013. It includes underfills for flip chip and packages. The increased use of underfills for CSPs and WLPs are likely to pass the drop test in high-end mobile devices.

Wafer-level dielectrics were $94 million market in 2013. Materials and structures are likely to enhance board-level reliability performance.

Die-attach materials has over a dozen suppliers. Hitachi Chemical and Henkel account for major share of total die attach market. New players are continuing to emerge in China and Korea. Stacked-die CSP package applications have been increasing. Industry acceptance of film (flow)-over-wire (FOW) and dicing die attach film (DDF) technologies are also happening.

Semicon West 2014: SEMI World Fab forecast report

Christian Gregor Dieseldorff, senior analyst, Industry Research & Statistics  Group at SEMI, presented the SEMI World Fab Forecast at the recently held Semicon West 2014, as part of the SEMI/Gartner Market Symposium on July 7.

Scenarios of fab equipment spending over time has been  20-25 percent in 2014, and 10-15 percent in 2015. At this time, worldwide fab equipment spending is about same in 1H14 vs 2H14. As for fab construction projects, 2013 was a record year with over $9 billion.

New fabs: construction spending (front end cleanrooms only!)
2013: record year with over $9 billion.
2014: -22 percent to -27 percent (~$6.6 billion)
2015: -22 percent to -30 percent (~$5 billion +/-).

Fab equipment spending front end (new and used)
2014: 20 percent to 25 percent (~$35 billion to $36 billion) – if $35 billion, then third largest on record.
2015: 10 percent to 15 percent (~$40 billion) – if $40 billion, then largest in record.

Installed capacity for front end fabs (without discretes)
2014: 2 to 3 percent
2015: 3 to 4 percent
Future outlook beyond 2015: less than 4 percent.

SEMI World Fab Forecast report status and activity outlined that there were 1,148 front end facilities (R&D to HVM) active and future. Also,
* There are 507 companies (R&D to HVM).
* Including 249 LEDs and Opto facilities active and future.
* There are 60 future facilities starting HVM in 2014 or later.
* Major investments (construction projects and/or equipping): 202 facilities in 2014, 189 facilities in 2015.

A slow down of fab closures is expected from 2015 to 2018 for 200mm fabs and 150mm fabs.

Semiconductor capital spending outlook 2013-18: Gartner

At Semicon West 2014, Bob Johnson, VP Research, Gartner, presented the Semiconductor Capital Spending Outlook at the SEMI/Gartner Market Symposium on July 7.

First, a look at the semiconductor revenue forecast: it is likely to grow at a 4.3 percent CAGR from 2013-2018. Logic continues to dominate, but growth falters. As per the 2013-2018 CAGRs, logic will be growing 3.5 percent, memory at 4.5 percent, and other at 6.3 percent.

As for the memory forecast, NAND should surpass DRAM. At 2013-2018 CAGRs, DRAM should grow -1.1 percent, while NAND should grow 10.8 percent. Smartphone, SSD and Ultramobile are the applications driving growth through 2018. SSDs are powering the NAND market.

Among ultramobiles, tablets should dominate through 2018. They should also take share from PCs. Next, smartphones have been dominating mobile phones.

Looking at the critical markets for capital investment, smartphones are the largest growth segment, but have been showing signs of saturation. The revenue growth could slow dramatically by 2018. Ultramobiles have the highest overall CAGR, but at the expense of PC market. Tablets are driving down semiconductor content. Desktop and notebook PCs are a large, but declining market. This also requires critical revenue to fund logic capex. Lastly, SSDs are driving NAND Flash growth. The move to data centers is driving sustainable growth.

In capital spending, memory is strong, but logic is weak through 2018. The 2014 spending is up 7.1 percent, driven by strong memory market. Strength in NAND spending will drive future growth. Note that memory oversupply in 2016 can create next cycle. NAND is the capex growth driver in memory spending.

The major semiconductor markets, which justify investment in logic leading edge capacity, are now running out of gas. Ultramobiles are cannibalizing PCs, smartphones are saturating and both are moving to lower cost alternatives. It is increasingly difficult to manufacture complex SoCs successfully at the absolute leading edge. Moore’s Law is slowing down, while costs are going up.

Breakthrough technologies (i.e., EUV) are not ready when needed. Much of the intelligence of future applications is moving to the cloud. The data centers' needs for fast, low power storage solutions are creating sustainable growth for NAND Flash.

The traditional two-year per node pace of Moore’s Law will continue to slow down. Only a few high volume/high performance applications will be able to justify the costs of 20nm and beyond. Whether this will require new or upgraded capacity is uncertain. 28nm will be a long lived node as mid-range mobility products demand higher levels of performance. Finally, the cloud will continue to grow in size and influence creating demand for new NAND Flash capacity and technology.

How Intel competes on today’s fabless ecosystem?

The SEMI/Gartner Market Symposium was held Semicon West 2014 at San Francisco, on July 7. Am grateful to Ms. Becky Tonnesen, Gartner, and Ms Agnes Cobar, SEMI, for providing me the presentations. Thanks are also due to Ms Deborah Geiger, SEMI.

Dean Freeman, research VP, Gartner, outlined the speakers:

• Sunit Rikhi, VP, Technology and Manufacturing Group, GM, Intel Custom Foundry Intel, presented on Competing in today’s Fabless Ecosystem.

• Bob Johnson, VP Research, Gartner, presented the Semiconductor Capital Spending Outlook.

• Christian Gregor Dieseldorff, director Market Research, SEMI, presented the SEMI World Fab Forecast: Analysis and Forecast for Fab Spending, Capacity and Technology.

• Sam Wang, VP Research Analyst, Gartner, presented on How Foundries will Compete in a 3D World.

• Jim Walker, VP Research, Gartner, presented on Foundry versus SATS: The Battle for 3D and Wafer Level Supremacy.

• Dr. Dan Tracy, senior director, Industry Research & Statistics, SEMI, presented on Semiconductor Materials Market Outlook.

Let's start with Sunit Rikhi at Intel.

As a new player in the fabless eco-system, Intel focuses on:
* The value it brings to the table.
* How it delivers on platforms of capability and services.
* How it leverage the advantages of being inside the world’s leading Integrated Device Manufacturer (IDM)
* How it face the challenges of being inside the world’s leading IDM.

Intel has leadership in silicon technologies. Transistor performance per watt is the critical enabler for all. Density improvements offset wafer cost trends. Intel currently has ~3.5-year lead in introducing revolutionary transistor technologies.

In foundry capabilities and services platforms, Intel brings differentiated value on industry standard platforms. 22nm was started in 2011, while 14nm was started in 2013. 10nm will be starting in 2015. To date, 125 prototype designs have been processed.

Intel offers broad capability and services on industry standard platforms. It also has fuller array of co-optimized end-to-end services. As for the packaging technology, Intel has been building better products through
multi-component integration. Intel has also been starting high on the yield learning curve.

Regarding IDM challenges, such as high-mix-low-volume configuration, Intel has been doing configuration optimization in tooling and set-up. It has also been separating priority and planning process for customers. Intel has been providing an effective response for every challenge.

Some of Intel Custom Foundry announced customers include Achronix, Altera, Microsemi, Netronome, Panasonic and Tabula.

What's the future of MEMS?

What does the future hold for MEMS? How can the MEMS indistry stay profitable and innovative in the next five years? The MEMS market is still in a dynamic growth with an estimated 12.3 percent CAGR over 2013-2019 in $US value, growing from $11.7 billion in 2013 to $24 billion in 2019.

This growth, principally driven by a huge expansion of consumer products, is mitigated by two main factors. First, due to a fierce competition based on pricing, the average selling prices (ASPs) are continuously decreasing.

Second, innovation is slow and incremental, as no new devices have been successfully introduced on the market since 2003.  Fierce competition based on pricing in now ongoing putting thus extreme pressure on device manufacturers.

Some trends are still impacting MEMS business. These are:

* Decrease of price in consumer electronics; ASP of MEMS microphones.
* Component size is still decreasing.

However, successful companies are still large leaders in distinct MEMS categories, such as STMicroelectronics, Knowles, etc. But maintaining growth in consumer electronic applications remains a challenge.

The market for motion sensor in cell phones and tablets is large and continuously expanding. Discrete sensors still decline, but will still be used in some platforms (OIS function for gyros). Next, 6- and 9-axis combos should grow rapidly. Because of strong price pressure and high adoption rate, the total market will stabilize from 2015.

STMicroelectronics, InvenSense and Bosch are still leaders in 3-axis gyros and 6-axis IMUs. It seems difficult for new players to compete and be profitable in this market. The automotive, industrial and medical applications of MEMS are also drivingthe growthof the MEMS business. MEMS for automotive will grow from $2.6 billion in 2012 to $3.6 billion in 2018 with 5 percent CAGR.

MEMS industry is big and growing. Strong market pull observed for sensors and actuators in cell phones, automotive, medical, industrial.

• Not limited to few devices. A new wave of MEMS is coming!

• Component and die size are still being optimized while combo approaches become mainstream. And several disruptive technology approaches are now in development to keep going in term of size and price decrease.

• But the MEMS industry has not solved a critical issue: how to increase the chance of new devices to enter the market?

–RF switch, autofocus, energy harvesting devices, fuel cells… are example of devices still under development after more than 10 years of effort.
–How to help companies to go faster and safer on the market with new devices?

Is GaN-on-Si disruptive technology?

The masse adoption of GaN on Si technology for LED applications remains uncertain. Opinions regarding the chance of success for LED-On-Si vary widely in the LED industry from unconditional enthusiasm to unjustified skepticism. Although significant improvements have been achieved, there are still some technology hurdles (such as performance, yields, CMOS compatibility, etc.).

The differential in substrate cost itself is not enough to justify the transition to GaN on Si technology. The main driver lies in the ability to manufacture in existing, depreciated CMOS fabs in 6” or 8”. For Yole Développement, if the technology hurdles are cleared, GaN-on-Si LEDs will be adopted by some LED manufacturers, but will not become the industry standard.

Yole is more optimistic about the adoption of GaN on Si technology for power GaN devices. Contrary to LED industry, where GaN on Sapphire technology is the main stream and presents a challenging target, GaN on Si will dominate the GaN based power electronics applications. Although the GaN based devices remain more expensive than Si based devices, the overall cost of GaN device for some applications are expected to be lower three years from now according to some manufacturers.

In 2020, GaN could reach more than 7 percent of the overall power device market and GaN on Si will capture more than 1.5 percent of the overall power substrate volume, representing more than 50 percent of the overall GaN on Si wafer volume, subjecting to the hypothesis that the 600 V devices would take off in 2014-2015.

GaN targets a $15 billion served available device market. GaN can power 4 families of devices and related applications. These are blue and green laser diodes, LEDs, power electronics and RF.

Regarding GaN-on-Si LED, there will be no more than 5 percent penetration by 2020. As for GaN-on-GaN, it will be less than 2 percent. Yole considers that the leading proponents of LED-On-Si will successful and eventually adopt Si for all their manufacturing. Those include Bridgelux/Toshiba, Lattice Power, TSMC and Samsung. It expects that Silicon will capture 4.4 percent of LED manufacturing by 2020.

GaN wafer could break through the $2000 per 4” wafer barrier by 2017 or 2018, enabling limited adoption in applications that require high lumen output other small surfaces.

Plunify’s InTime helps FPGA design engineers meet timing and area goals!

Engineers designing FPGA applications face many challenges. Starting from setting up the environment, to handling multiple tools, tackling design problems and analyzing results.

Using Plunify's automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.

Kirvy Teo said: What happens when you need to close timing in FPGA design and still can't get it to work? Here is a new way to solve that problem - machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending "strategies".

Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.

One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can't run seeds on a design with bad timing scores.

However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!

How has Plunify been doing this year so far? Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them "BCC" - Big Chinese Corporations.

Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.

Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.

What's the future path likely to be? Teo added: "Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.

"First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!

"As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don't know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.

Why would FPGA providers take up the solution? The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current  in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about "Getting better results without touching your RTL code!"

Optic2Connect develops software for photonics!

Optic2Connect will be present at this year’s DAC. I caught up with Sean Seah, project manager, to find out more.

First, what’s the company’s X factor and why? (What is it that makes your offering special and noteworthy – how are you different from competitors)?

Optic2Connect develops software solutions for the photonics industry. The demand to manage high volumes of data in networks, especially with the current smart-phone and cloud computing trend, has increased tremendously. As design gets more complex, simulation tools need to scale with regard to fidelity and accuracy.

Currently, photonic designers, scientists, and fabrication engineers adopt an approximated approach from the electrical data to build an equivalent optical model, hence losing on device physics details. At the same time the process is long as the model needs to be described block-by-block with denser blocks representing a more detailed model. Our competitors are well established in their respective domains, electrical or optical, but they are strong in their own respective fields. However, intimate knowledge in both are essential to fully understand this newer generation of photonic devices. Failure to understand fully results in false results from the manufacturing.

With patented know-how, Optic2Connect provides software solutions that SOLVES this pertinent challenge. It maps accurately simulations from one domain to another, e.g. electrical to optical. This technology has been developed by a team of researchers at A*Star – Singapore Public Research Institute. The technology overcomes error-prone and detailed oriented simulation setups. We demonstrated the ability to map without losing any fidelity in the simulation files.

Optic2Connect’s IP differs from its competitors because it simulates directly from the beginning device processing, to electrical device performance until the final high-speed optical eye diagram. This is in stark contrast to the usual method of representing their operation using simplified transfer functions.

Furthermore, the Optic2Connect design flow uses the same reliable tools and processes from the semiconductor industry that are fully compatible with the Complementary Metal Oxide Semiconductor (CMOS) fabrication process of silicon microelectronics. This design flow uses standard tools libraries, device models especially for active components such as modulators, and simulation of these components incorporating the models.

How have you been doing this year so far? Seah said: “It has been excellent! We are racing to complete our product prototypes and we secured a contract from an MNC and another from universities.”

What’s the future path likely to be? Seah added: “We intend to further validate our prototype with our partners from industry and academia, and integrating advanced modulation formats into our solutions. We want to offer a fully integrated solution for photonic devices to our customers. Our goal is to offer a one-stop solution for leading integrated-circuit (IC) manufacturers!”

Why this name? You sounded like a telecom company? Seah said: “We strongly believe the future of communications is via optics which has the ability to circumvent the data bottleneck issues. Optic2Connect is meant to offer connect using optical communications. Our goal is a one-stop solution for optical connections. “

How will the solution significantly shorten product time-to-market and reduce development costs of photonics devices?

For complex photonics devices, minute changes to design parameters are significant and could affect loss performance, and operating voltage requirements. One common approach in the industry today is to physically build the variations into multiple device / runs and test them out. Each run cost is the range of hundreds of thousands and consume precious time. Especially, if the first batch of devices do not meet required parameters and additional batches are required. This cost both money and time, which in turn is more money.

Hence, Optic2Connect provides an elegant solution with our accurate modelling and simulation solutions, this accelerates manufacturing prototypes and at much lower production costs. Our software solutions provide a 10x improvement in time reduction and time to market. Further, our cloud solution overcomes traditional problems of insufficient servers / licenses, especially during periods of peak demand.

Metro450 Conference 2014 discusses all things 450mm wafers!

Thanks to the Enable450 newsletter, sent out by Malcolm Penn, CEO, Future Horizons, here is a piece on the Metro450 Conference 2014, held earlier this year in Israel.

Metro450 is an Israel-based consortium with the goal of helping the metrology companies advance in their fields. The consortium’s members include metrology and related companies, as well as academics who support these companies by performing basic research.

The conference was sponsored by the Israeli Chief Scientist Office, Applied Materials Israel and Intel. There were several goals for the conference: to provide an opportunity for industry leaders as well as academicians to meet and discuss the latest developments in the world of metrology, to present these advances to audiences which would normally not be privy to such information, and to learn more about the international effort in 450mm wafer technology.

Over 200 people attended this conference from Israeli companies and academia, as well as from Europe and the United States. Israeli companies included Applied Materials, Jordan Valley, Nova, KLA, Zeiss Israel, and others. Academic members included researchers from the leading Israeli universities, including the Technion, Tel-Aviv University. and Haifa University.

European companies were represented by ENIAC, as well as large corporations such as ASML as well SME-based companies. The G450C consortium, based in Albany, N.Y. was also well represented at this conference.

Some of the highlights of the conference included scientific discussions of different metrology methods, and their adjunct requirements, such as improved rapid wafer movement, improved sampling methods and fast computing. Presentations also included an overview of the advances necessary to move the industry forward, optical CD metrology, x-ray metrology, and novel piezo-based wafer movement.

A panel discussed various broad industry trends, including the timeline of 450mm wafers, European programs and the Israeli programs. International speakers discussed the European technology model, risk mitigation of 450 through collaborations, 450 collaborative projects under ENIAC, 450mm wafer movement challenges and metrology challenges beyond 14nm.

This second annual Metro450 conference took place this January at the Technion, Israel.

Renesas aims to increase its MCU share in India

Renesas Electronics recently opened its India subsidiary in Bangalore. Elaborating, Sunil Dhar, managing director of Renesas Electronics India said: "We are glad to announce the opening of Renesas Electronics India Pvt Ltd, a wholly-owned subsidiary of Renesas Electronics Singapore Pte Ltd., located in Bangalore.

"Since 2010, Renesas has been providing technical product support to its customers here via branch offices in Bangalore, Delhi and Mumbai. As part of its expansion plan, Renesas will turn our said branches into a full subsidiary.

"The branch office setup served us well when the organization was small and its role was limited. In order to expand further in terms of opening more offices in India for close customer support, and to be able to provide wider services to customers in India like reference software, hardware, reference solutions which would be developed in India, it would require us to have a permanent establishment here.

"Through this new company, we aim to expand business by providing the best solution offerings and technical support as well as a regional systems solution development expertise to the Indian market."

How does the India R&D team play a role in global innovation and where do you see Renesas Electronics in India five years from now?

He said that over 50 percent of the Renesas India team is application development or field engineers armed with knowledge of embedded hardware and software development and support.

In order to expand the footprint in Indian markets, Renesas plans to build up a strong application engineering team. India Application engineering team will engage with the Renesas headquarters, regional offices to develop new products and solutions dedicated for emerging countries, including India.

The application engineering team and the future solution centre aim to survey the market for solution needs, prepare India designed solutions fitting the price points and specifications points as required in the Indian market. Along with the customers, the team also intends to collaborate with the design houses to create innovative solutions addressing upcoming needs of the market. Our goal is to become the most trusted semiconductor solution provider in India.

What are the India-centric solutions that would be developed from the India Application Engineering team?

Dhar added that the needs of emerging markets are usually different in both specifications as well as price points. By providing dedicated local support via the new company, and with a focus on industrial and automotive applications for two- and four-wheelers, Renesas aims to increase its MCU share in India and expand its solution offerings with rich lineup of kit solutions (MCU + SoC + power devices) and platform reference boards (boards with complete ecosystem including devices and software) to provide customers a shorter time-to-market.

The team will initially focus on automotive and particularly, two-wheeler solutions. The intention is to expand the scope of the application engineering team’s activity to industrial and consumer appliances in near term.

What is the overall India employee strength? How are the investment plans looking up?

Dhar said: "In order to expand our footprint in Indian markets, we will double our headcount in near term.  Currently, we are just under 30 staff and over 50 percent of us are application development or field engineers armed with the knowledge of embedded hardware and software development and support. Upon setting up the organization in Sales and Marketing roles in the initial days, we also have plans to announce the setting up of a Solutions Centre in India to develop reference application solutions to enable our customers to use our devices.

"We are intending to invest in lab, infrastructure setup and expansion of activities in the next three to five years. Additionally, we are also considering investing towards 3rd party and IDH for enlarged business  engagement."

Trends driving automotive market in India
Regarding trends driving the automotive market in India, Dhar said that Renesas focusses on three business segments – automotive, industrial and home, OA and ICT. Renesas holds more than 40 percent global market share for automotive MCU business. Our target applications for automotive segment are automotive control and automotive infotainment and network.

Renesas has dedication applications solutions for integrated cockpit through system on chip, R-car ecosystem collaboration solution for e-mobility and automotive analog and power devices for driving, steering and braking.

As semiconductor technologies evolved, it has enabled automakers to integrate multiple applications on a single chip significantly reducing the board area; thus optimizing performance and adding new features for comfort, safety and infotainment. Power technologies have brought energy efficiency, limiting power consumption in vehicles. Advancements in process technologies will continue to drive the auto industry in the coming years.

Renesas, for instance, developed the industry's first 28nm flash memory IP for MCUs and the first semiconductor supplier to move from 40nm to 28nm process technology.

"Trends driving auto industry in India and globally are more of less the same. However, for India market, we see a specific demand for two-wheeler solutions and that is our target in coming years," he concluded.

Lastly, I must take the opportunity to thank Ms Shweta Dhadiwal-Baid and Ms Sharmita Mandal for making this happen! ;)

Set up strong methodology teams to create better verification infrastructure: Synopsys

This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as:

* Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution.

* No or very low investment in building better verification environments (based on best/new methodologies and best practices); instead maintaining older verification environments.

* Compromising on verification completeness because of tape out pressures and time-to-market considerations.

Would you agree that many companies STILL do not know how to verify a chip?

It could be true for smaller companies or start-ups, but most of the major semiconductor design engineers know about the better approaches/methodologies to verify their chips. However, they may not be investing in implementing the new methodologies for multiple reasons and may instead continue to follow the traditional flows.

How are companies trying to address those? One way to address these mistakes would be to set up strong methodology teams to create a better verification infrastructure for future chips. However, few companies are doing this.

Are companies realizing this and building an infrastructure that gets you business advantage? According to him, some companies do realize this and are investing in building a better infrastructure (in terms of better methodology and flows) for verification.

When should good verification start -- after design; as you are designing and architecting your design environment?

He said that good verification starts as soon as we start designing and architecting the design. Verification leads should start discussing the verification environment components with the lead architect and also start writing the verification plan.

Are folks mistaking by looking at tools and not at the verification process itself? He noted that tools play a major role in the effectiveness of any verification process, but we still see a lot of scope in methodology improvements beyond the tools.

What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities? As per Ghosh, there is not a single full-proof recipe for a ‘right’ verification path. It depends on multiple factors, including whether the design is a new product or derivative, the design application etc. But yes, it is very important to do comprehensive verification planning before starting the verification process.

How is Synopsys addressing this? Synopsys is said to be building a comprehensive, unified and integrated verification environment is required for today’s revolutionary SoCs and would offer a fundamental shift forward in productivity, performance, capacity and functionality.

Synopsys’ Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.

Verification Compiler includes:

* Better capacity and compile and runtime performance.
* Next-generation static and formal technology delivering performance improvement and the capacity to analyze a complete SoC (Property checking, LP, CDC, connectivity).
* Comprehensive low power verification solution.
* Verification planning and management.
* Next-generation verification IP and a deep integration between VIP and the simulation engine, which in turn can greatly improve productivity.  The constraint engine is tuned for optimal performance with its VIP library. It has integrated debug solutions for VIP so one can do protocol-level analysis and transaction-based analysis with the rest of the testbench.
* Support for industry standard verification methodologies.
* X-propagation simulation with both RTL and low power simulations.
* Common debug platform with better debug technology having new capabilities, tight integrations with simulation, emulation, testbench, transaction debug, power-aware debug , hw/sw debug, formal, VIP and coverage.

Top verification recommendations
What would be Synopsys' top five recommendations for verification?

* Spend a meaningful amount of time and effort on verification planning before execution.

* Continuously invest in building a better verification infrastructure and methodologies across the company for better productivity.

* Collaborate with EDA companies to develop, evaluate and deploy new technologies and flows, which can bring more productivity to verification processes.

* Nurture fresh talent through regular on and off-the-job trainings (on flows, methodologies, tools, technology).

* Conduct regular reviews of the completed verification projects with the goal of trying to improve the verification process after every tapeout through methodology enhancements.

Cadence: Plan verification to avoid mistakes!

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let's try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: "I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

"For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip."

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: "Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements."

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there's verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

Five recommendations for verification: Dr. Wally Rhines

It seems to be the season of verification. The Universal Verification Methodology (UVM 1.2) is being discussed across conferences. Dennis Brophy, director of Strategic Business Development, Mentor Graphics, says that UVM 1.2 release is imminent, and UVM remains a topic of great interest.

Biggest verification mistakes
Before I add Dennis Brophy’s take on UVM 1.2, I discussed with Dr. Wally Rhines, chairman and CEO, Mentor Graphics Corp. the intricacies regarding verification. First, I asked him regarding the biggest verification mistakes today.

Dr. Rhines said: “The biggest verification mistake made today is poor or incomplete verification planning. This generally results in underestimating the scope of the required verification effort. Furthermore, without proper verification planning, some teams fail to identify which verification technologies and tools are appropriate for their specific design problem.”

Would you agree that many companies STILL do not know how to verify a chip?

Dr. Rhines added: “I would agree that many companies could improve their verification process. But let’s first look at the data. Today, we are seeing that about 1/3 of the industry is able to achieve first silicon success. But what is interesting is that silicon success within our industry has remained constant over the past ten years (that is, the percentage hasn’t become any worse).

“It appears that, while design complexity has increased substantially during this period, the industry is at least keeping up with this added complexity through the adoption of advanced functional verification techniques.

“Many excellent companies view verification strategically (and as an advantage over their competition). These companies have invested in maturing both their verification processes and teams and are quite productive and effective. On the other hand, some companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.”

How are companies trying to address those?
According to him, the recent Wilson Research Group Functional Verification Study revealed that the industry is maturing its verification processes through the adoption of various advanced functional verification techniques (such as assertion-based verification, constrained-random simulation, coverage-driven techniques, and formal verification). 

Complexity is generally forcing these companies to take a hard look at their existing processes and improve them.

Getting business advantage
Are companies realizing this and building an infrastructure that gets you business advantage?

He added that in general, there are many excellent companies out there that view verification strategically and as an advantage over their competition, and they have invested in maturing both their verification processes and teams. On the other hand, some other companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.

When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment?

Dr. Rhines noted: “Just like the design team is often involved in discussion during the architecture and micro-architecture planning phase, the verification team should be an integral part of this process. The verification team can help identify architectural aspects of the design that are going to be difficult to verify, which ultimately can impact architectural decisions.”

Are folks mistaken by looking at tools and not at the verification process itself? What can be done to reverse this?

He said: “Tools are important! However, to get the most out of the tools and ensure that the verification solution is an efficient and repeatable process is important. At Mentor Graphics, we recognize the importance of both. That is why we created the Verification Academy, which focuses on developing skills and maturing an organization’s functional verification processes.”

What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities?

Dr. Rhines said: “During verification planning, too many organizations focus first on the “how” aspect of verification versus the “what.” How a team plans to verify its designs is certainly important, but first you must identify exactly what needs to be verified. Otherwise, something is likely to slip through.

“In addition, once you have clearly identified what needs to be verified, it’s an easy task to map the functional verification solutions that will be required to productively accomplish your verification goals. This also identifies what skill sets will need to be developed or acquired to effectively take advantage of the verification solutions that you have identified as necessary for your specific problem.”

How is Mentor addressing this situation?
Mentor Graphics’ Verification Academy was created to help organizations mature their functional verification processes—and verification planning is one of the many excellent courses we offer.

In addition, Mentor Graphics’ Consulting provides customized solutions to technical challenges on real projects with real schedules. By helping customers successfully integrate advanced functional verification technologies and methodologies into their work flows, we help ensure they meet their design and business objectives.

Five recommendations for verification
Finally, I asked Dr. Rhines what would be the top five recommendations for verification?

Here are the five recommendations for verification from Dr. Rhines:

* Ensure your organization has implemented an effective verification planning process.

* Understand which verification solutions and technologies are appropriate (and not appropriate) for various classes of designs.

* Develop or acquire the appropriate skills within your organization to take advantage of the verification solutions that are required for your class of design.

* For the SoC class of designs, don’t underestimate the effort required to verify the hardware/software interactions, and ensure you have the appropriate resources to do so.

* For any verification processes you have adopted, make sure you have appropriate metrics in place to help you identify the effectiveness of your process—and identify opportunities for process improvements in terms of efficiency and productivity.