E450EDL – European 450mm equipment demo line

Malcolm Penn, chairman and CEO, Future Horizons, sent me the Enable 450 newsletter. The goal of the Enable 450 is: Co-ordination Action to enable an effective European 450 mm Equipment and Materials Network. Here, I am presenting a bit about the E450EDL – European 450mm Equipment demo line.

The aim of the ENIAC E450EDL key enabling technology pilot project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition that started with the ENIAC JU EEMI450 initiative and proceeded with subsequent projects funded with public money, amongst others NGC450, SOI450, EEM450PR.

The demo line resulting from this project will be such that it will enable first critical process module development by combining imec infrastructure with tools remaining at the site of the manufacturers (distributed pilot line). Multi-site processing will allow partners to participate in the world first 450mm integration studies and will be enabled by the controlled exchange of 450mm wafers between different sites.

The consortium comprises 41 members (from 11 different European countries) with many SMEs and research institutes. The project is organized in five technical work packages and a work package on management and co-ordination.

In the work package on integration and wafer processing first critical modules will be developed and will demonstrate the feasibility of processing on 450mm wafers. The main objective in the work package on lithography is to develop a wafer stage test-rig, which can be implemented into the pilot line system.

In the work package on front end equipment several tools will be developed such as a plasma ion implant module, a plasma dry etch module, a RTP system and a single wafer cleaning system.

Furthermore, in the dedicated work package on metrology 450mm metrology tool types will be developed for amongst others dielectric film thickness and composition measurements, defect inspection, defect review and analysis, optical critical dimensions (CD), overlay (mask and wafer) and 3D metrology.

Finally, from the work package on wafer handling and automation a set of equipment will be provided to support the demo line operations, and facilitate the R&D dedicated to process and metrology modules.
The project will last 36 months beginning on 1st of October 2013. The budget has been given at €204.6 million of which the ENIAC JU will fund €30.8 million. This project is still considering new members so if you are interested please contact ASML.

Inertial micropump technology for microfluidic apps

At a MEMS Industry Group seminar in Orlando, US, Alexander Govyadinov, lead technologist, Hewlett-Packard Printing & Technology Development Organization said microfluidics looks at the movement of small amounts of fluids through microchannels.

The current microfluidic applications include pharmaceutical and life science research, clinical and veterinary diagnostics, human point-of-care, analytical devices, environment and industrial testing, and inhalers, micropumps and microneedles.

The microfluidic segment has been growing at 20 percent CAGR. By 2016, the $4.7 billion market size refers to the over 1 billion microfluidic chips and substrates. The GM for synthetic biology reached $1 billion in 2012.

Every fluidic system needs a pump. Although external pumps are commonly used, there is lack of simple, cheap and easy-to-integrate mcro-pumps.

There is passive capillary pump operation using capillaty retention valve (CRV). In a capillary-driven microfluidic device the chip is composed of microfluidic functional elements. There are rotary pumps as well. Rotating gears can be hard to integrate and require strong external actuators. Mostly, external pumps are available. There are pneumatic/membrane micropumps as well as external piezo pumps and active pumps.

In a thermal inkjet (TIJ), the voltage pulse heats the resistor and boils the fluid. Once, the droplet has been ejected, the chamber is refilled by capillary forces. HP has an inertial pump for microfluidics. There exists a computational fluid dynamics (CFD) inertial pump model. An optimal resistor location is available. There are 2mmx512 pump-channel arrays.

Vison for future micropump applications include generic fluidic network with reversible pumps. Pumps' densities can be up to 1000 per inch2. There are concepts such as polymerase chain reactor and u-calorimeter total analysis system.

Microfluidics is a growing field. Inertial pump is a new way to move fluids through microchannels.

Now, I’m on Wikipedia! ;) Thanks everyone!! :)

Today is Holi, the festival of colors. Well, it added some more color to my life as I was told that I have been listed on Wikipedia!  You can see it here! ;)

I don’t really know who has added me there, or where they are getting all of their information. All I can humbly say is: thanks a lot, very sincerely, to Wikipedia! :)

Wikipedia has said I’ve been staying at my Delhi residence since 1984! Well, that’s the year my father, late, Pramode Ranjan Chakraborty, bought this house. Later, in 1986, he, along with my mother, late Mrs Bina Chakraborty, moved to this house.

Why this huge gap in our buying the house and moving in? Well, not many folks know that my parents met with a near fatal accident on Jan. 27, 1986 in the early hours of the day at New Delhi. They were going home by an auto-rickshaw to our home at Greater Kailash-II, New Delhi, when an Ambassador car rammed into their auto-rickshaw full on!

That’s also the day my life changed completely! I was still a student, playing cricket with friends, when my aunt called us from Delhi. We rushed to Delhi, to find our parents badly injured! I personally had to say goodbye to cricket, and turned attention to finding work. I finally moved to Delhi in Nov. 1987 and that's where my entire life started!

It has been a great ride ever since! All the hard work done seems to have paid off. First, I must mention Gratian Vas, who took me in at Holy Faith International back in 1988. My first brush with electronics was at SBP Consultants & Engineers a year later, followed by Electronics For You. However, it was at DiSyCom magazine, under Arun Bhattacharjee, where I learned the ropes.

Later, I was hired by late Ms Rashmi Bhushan to write for electronic components magazine published by Asian Sources Media. That’s when my life changed significantly! Not only did Asian Sources Media, now, Global Sources, hire me as the full-time telecom editor  and take me to Hong Kong, it gave me first-hand view of China and how it grew in the world of electronics! It has been a fascinating journey ever since!

Thereafter, it was at Reed Elsevier, in Singapore, where I had the late Ian Shelley, Michael Tan, Paul Beh and Swee Heng Tan for company. Everywhere, I learned a lot! That’s what I continue to do even today!

The world can give me as many awards and folks can call me anything, but I shall always remain, yours truly!  :)

What technology SoC engineers need for next-gen chips?

About 318 engineers and managers completed a blind, anonymous survey on 'On-Chip Communications Networks (OCCN), also referred to as an “on-chip networks”, defined as the entire interconnect fabric for an SoC. The on-chip communications network report was done by Sonics Inc. A summary of some of the highlights is as follows.

The average estimated time spent on designing, modifying and/or verifying on-chip communications networks was 28 percent (for the respondents that knew their estimate time).

The two biggest challenges for implementing OCCNs were meeting product specifications and balancing frequency, latency and throughput. Second tier challenges were integrating IP elements/sub-systems and getting timing closure.

As for 2013 SoC design expectations, a majority of respondents are targeting a core speed of at least 1 GHz for SoCs design starts within the next 12 months, based on those respondents that knew their target core speeds. Forty percent of respondents expect to have 2-5 power domain partitions for their next SoC design.

A variety of topologies are being considered for respondents’ next on-chip communications networks, including NoCs (half), followed by crossbars, multi-layer bus matrices and peripheral interconnects; respondents that knew their plans here, were seriously considering an average of 1.7 different topologies.

Twenty percent of respondents stated they already had a commercial Network-on-Chip (NoC) implemented or plan to implement one in the next 12 months, while over a quarter plan to evaluate a NoC over the next 12 months. A NoC was defined as a configurable network interconnect that packetizes address/data for multicore SoCs.

For respondents who had an opinion when commercial Networks-on-Chip became an important consideration versus internal development when implementing an SoC, 43 percent said they would consider commercial NoCs at 10 or fewer cores; approximately two-thirds said they would consider commercial NoCs at 20 or fewer cores.

The survey participants’ top three criteria for selecting a Network on Chip were: scalability-adaptability, quality of service and system verification, followed by layout friendly, support for power domain partitioning. Half of respondents saw reduced wiring congestion as the primary reason to use virtual channels, followed by increased throughput and meeting system concurrency with limited bandwidth.

Focus on SiC power electronics business 2020

SiC is currently implemented in several power systems and is gaining momentum and credibility.

Yole Developpement stays convinced that the most pertinent market for SiC lands in high and very high voltage (more than 1.2kV), where applications are less cost-driven and where few incumbent technologies can’t compete in performance. This transition is on its way as several device/module makers have already planned such products at short term.

Thus, even though EV/HEV skips SiC, industry could expand among other apps. Now, the only question remains: Is there enough business to make so many contenders live decently? Probably, yes, as green-techs are also expanding fast, strongly requesting SiC. But, any newcomers should carefully manage strategy and properly size capex according to the market size.

Power electronics industry outlook
Electronics systems were worth $122 billion in 2012, and will likely grow to $144 billion by 2020 at a CAGR of 1.9 percent. Power inverters will grow from $41 billion in 2012 to over $70 billion by 2020 at a CAGR of 7.2 percent. Semiconductor power devices (discretes and modules) will grow from $12.5 billion in 2012 to $21.9 billion by 2020 at a CAGR of 7.9 percent. Power wafers will grow $912 million in 2012 to $1.3 billion by 2020 at a CAGR of 5.6 percent.

Looking at the power electronics market in 2012 by application and the main expectations to 2015, computer and office will account for 25 percent, industry and energy 24 percent, consumer electronics 18 percent, automotive and transport 17 percent, telecom 7 percent and others 9 percent.

The main trends expected for 2013-2015 are:
* Significant increase of automotive sector following EV and HEV ramp-up.
* Renewable energies and smart-grid implementation will drive industry sector ramp-up.
* Steady erosion of consumer segment due to pressure on price (however, volumes (units) will keep on increase).

The 2011 power devices sales by region reveals that overall, Asia is still the landing-field for more than 65 percent of power products. Most of the integrators are located in China, Japan or Korea. Europe is very dynamic as well with top players in traction, grid, PV inverter, motor control, etc. Asia leads with 39 percent, followed by Japan with 27 percent, Europe with 21 percent and North America with 13 percent.

The 2011 revenues by company/headquarter locations reveals that the big-names of the power electronics industry are historically from Japan. Nine companies of the top-20 are Japanese. There are very few power manufacturers in Asia except in Japan. Europe and US are sharing four of the top five companies. Japan leads with 42 percent, followed by Europe and North America with 28 percent each, respectively, and Asia with 2 percent.

Looking at the TAM comparison for SiC (and GaN), very high voltage, high voltage of 2kV and medium voltage of 1.2kV appear as a more comfortable area for SiC. The apps are less cost-driven and SiC added value is obvious. Low voltage from 0-900V is providing strong competition with traditional silicon technologies, SJ MOSFET and GaN. There are cost-driven apps.

Xilinx targets growing ASIC and ASSP gaps

Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.

To find out more about how are Xilinx's solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: "Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the Vivado Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.

"Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.

"Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp."

Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?

According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.

Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.

How are the solutions going to address the challenges with ASICs and ASSPs?

He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.

Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.

ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.

The biggest driver in the communications and networking markets is the insatiable need for bandwidth as traffic explodes well beyond the capabilities of networks to support that traffic.  However, the need is definitely not bandwidth or transmission capacity at any cost. It’s really a need for more bandwidth and more capacity at lower and lower cost in both wireless and wired networks.

Tensilica acquisition to broaden Cadence's IP portfolio

Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash.

With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto infotainment and home applications.

The Tensilica IP also complements industry-standard processor architectures, providing application-optimized subsystems to increase differentiation and get to market faster. Finally, over 200 licensees, including system OEMs and seven of the top 10 semiconductor companies, have shipped over 2 billion Tensilica IP cores.

Talking about the rationale behind Cadence acquiring Tensilica, Pankaj Mayor, VP and head of Marketing, Cadence Design Systems, said: "Tensilica fits and furthers our IP strategy - the combination of Tensilica's DPU and Cadence IP portfolio will broaden our IP portfolio.  Tensilica also brings significant engineering and management talent.  The combination will allow us to deliver to our customers configurable, differentiated, and application-optimized subsystems that improve time to market."

It is expected that the Cadence acquisition will see the Tensilica dataplane IP to complement Cadence and Cosmic Circuits' IP. Cadence had acquired Cosmic Circuits in February 2013.

What are the possible advantages of DPUs over DSPs? Does it also mean a possible end of the road for DSPs?

As per Mayor, DSPs are special purpose processors targeted to address digital signaling.  Tensilica's DPUs are programmable and customizable for a specific function, providing optimal data throughput and processing speed; in other words, the DPUs from Tensilica provide a unique combination of customized processing plus DSP. Tensilica's DPUs can outperform traditional DSPs in power and performance.

So, what will happens to the MegaChips design center agreement with Tensilica? Does it still carry on? According to Mayor, right now, Cadence and Tensilica are operating as two independent companies and therefire, Cadence cannot comment until the closing of the acquisition, which is in 30-60 days.