What's the future of MEMS?

What does the future hold for MEMS? How can the MEMS indistry stay profitable and innovative in the next five years? The MEMS market is still in a dynamic growth with an estimated 12.3 percent CAGR over 2013-2019 in $US value, growing from $11.7 billion in 2013 to $24 billion in 2019.

This growth, principally driven by a huge expansion of consumer products, is mitigated by two main factors. First, due to a fierce competition based on pricing, the average selling prices (ASPs) are continuously decreasing.

Second, innovation is slow and incremental, as no new devices have been successfully introduced on the market since 2003.  Fierce competition based on pricing in now ongoing putting thus extreme pressure on device manufacturers.

Some trends are still impacting MEMS business. These are:

* Decrease of price in consumer electronics; ASP of MEMS microphones.
* Component size is still decreasing.

However, successful companies are still large leaders in distinct MEMS categories, such as STMicroelectronics, Knowles, etc. But maintaining growth in consumer electronic applications remains a challenge.

The market for motion sensor in cell phones and tablets is large and continuously expanding. Discrete sensors still decline, but will still be used in some platforms (OIS function for gyros). Next, 6- and 9-axis combos should grow rapidly. Because of strong price pressure and high adoption rate, the total market will stabilize from 2015.

STMicroelectronics, InvenSense and Bosch are still leaders in 3-axis gyros and 6-axis IMUs. It seems difficult for new players to compete and be profitable in this market. The automotive, industrial and medical applications of MEMS are also drivingthe growthof the MEMS business. MEMS for automotive will grow from $2.6 billion in 2012 to $3.6 billion in 2018 with 5 percent CAGR.

MEMS industry is big and growing. Strong market pull observed for sensors and actuators in cell phones, automotive, medical, industrial.

• Not limited to few devices. A new wave of MEMS is coming!

• Component and die size are still being optimized while combo approaches become mainstream. And several disruptive technology approaches are now in development to keep going in term of size and price decrease.

• But the MEMS industry has not solved a critical issue: how to increase the chance of new devices to enter the market?

–RF switch, autofocus, energy harvesting devices, fuel cells… are example of devices still under development after more than 10 years of effort.
–How to help companies to go faster and safer on the market with new devices?

Is GaN-on-Si disruptive technology?

The masse adoption of GaN on Si technology for LED applications remains uncertain. Opinions regarding the chance of success for LED-On-Si vary widely in the LED industry from unconditional enthusiasm to unjustified skepticism. Although significant improvements have been achieved, there are still some technology hurdles (such as performance, yields, CMOS compatibility, etc.).

The differential in substrate cost itself is not enough to justify the transition to GaN on Si technology. The main driver lies in the ability to manufacture in existing, depreciated CMOS fabs in 6” or 8”. For Yole Développement, if the technology hurdles are cleared, GaN-on-Si LEDs will be adopted by some LED manufacturers, but will not become the industry standard.

Yole is more optimistic about the adoption of GaN on Si technology for power GaN devices. Contrary to LED industry, where GaN on Sapphire technology is the main stream and presents a challenging target, GaN on Si will dominate the GaN based power electronics applications. Although the GaN based devices remain more expensive than Si based devices, the overall cost of GaN device for some applications are expected to be lower three years from now according to some manufacturers.

In 2020, GaN could reach more than 7 percent of the overall power device market and GaN on Si will capture more than 1.5 percent of the overall power substrate volume, representing more than 50 percent of the overall GaN on Si wafer volume, subjecting to the hypothesis that the 600 V devices would take off in 2014-2015.

GaN targets a $15 billion served available device market. GaN can power 4 families of devices and related applications. These are blue and green laser diodes, LEDs, power electronics and RF.

Regarding GaN-on-Si LED, there will be no more than 5 percent penetration by 2020. As for GaN-on-GaN, it will be less than 2 percent. Yole considers that the leading proponents of LED-On-Si will successful and eventually adopt Si for all their manufacturing. Those include Bridgelux/Toshiba, Lattice Power, TSMC and Samsung. It expects that Silicon will capture 4.4 percent of LED manufacturing by 2020.

GaN wafer could break through the $2000 per 4” wafer barrier by 2017 or 2018, enabling limited adoption in applications that require high lumen output other small surfaces.

Plunify’s InTime helps FPGA design engineers meet timing and area goals!

Engineers designing FPGA applications face many challenges. Starting from setting up the environment, to handling multiple tools, tackling design problems and analyzing results.

Using Plunify's automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.

Kirvy Teo said: What happens when you need to close timing in FPGA design and still can't get it to work? Here is a new way to solve that problem - machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending "strategies".

Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.

One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can't run seeds on a design with bad timing scores.

However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!

How has Plunify been doing this year so far? Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them "BCC" - Big Chinese Corporations.

Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.

Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.

What's the future path likely to be? Teo added: "Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.

"First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!

"As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don't know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.

Why would FPGA providers take up the solution? The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current  in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about "Getting better results without touching your RTL code!"

Optic2Connect develops software for photonics!

Optic2Connect will be present at this year’s DAC. I caught up with Sean Seah, project manager, to find out more.

First, what’s the company’s X factor and why? (What is it that makes your offering special and noteworthy – how are you different from competitors)?

Optic2Connect develops software solutions for the photonics industry. The demand to manage high volumes of data in networks, especially with the current smart-phone and cloud computing trend, has increased tremendously. As design gets more complex, simulation tools need to scale with regard to fidelity and accuracy.

Currently, photonic designers, scientists, and fabrication engineers adopt an approximated approach from the electrical data to build an equivalent optical model, hence losing on device physics details. At the same time the process is long as the model needs to be described block-by-block with denser blocks representing a more detailed model. Our competitors are well established in their respective domains, electrical or optical, but they are strong in their own respective fields. However, intimate knowledge in both are essential to fully understand this newer generation of photonic devices. Failure to understand fully results in false results from the manufacturing.

With patented know-how, Optic2Connect provides software solutions that SOLVES this pertinent challenge. It maps accurately simulations from one domain to another, e.g. electrical to optical. This technology has been developed by a team of researchers at A*Star – Singapore Public Research Institute. The technology overcomes error-prone and detailed oriented simulation setups. We demonstrated the ability to map without losing any fidelity in the simulation files.

Optic2Connect’s IP differs from its competitors because it simulates directly from the beginning device processing, to electrical device performance until the final high-speed optical eye diagram. This is in stark contrast to the usual method of representing their operation using simplified transfer functions.

Furthermore, the Optic2Connect design flow uses the same reliable tools and processes from the semiconductor industry that are fully compatible with the Complementary Metal Oxide Semiconductor (CMOS) fabrication process of silicon microelectronics. This design flow uses standard tools libraries, device models especially for active components such as modulators, and simulation of these components incorporating the models.

How have you been doing this year so far? Seah said: “It has been excellent! We are racing to complete our product prototypes and we secured a contract from an MNC and another from universities.”

What’s the future path likely to be? Seah added: “We intend to further validate our prototype with our partners from industry and academia, and integrating advanced modulation formats into our solutions. We want to offer a fully integrated solution for photonic devices to our customers. Our goal is to offer a one-stop solution for leading integrated-circuit (IC) manufacturers!”

Why this name? You sounded like a telecom company? Seah said: “We strongly believe the future of communications is via optics which has the ability to circumvent the data bottleneck issues. Optic2Connect is meant to offer connect using optical communications. Our goal is a one-stop solution for optical connections. “

How will the solution significantly shorten product time-to-market and reduce development costs of photonics devices?

For complex photonics devices, minute changes to design parameters are significant and could affect loss performance, and operating voltage requirements. One common approach in the industry today is to physically build the variations into multiple device / runs and test them out. Each run cost is the range of hundreds of thousands and consume precious time. Especially, if the first batch of devices do not meet required parameters and additional batches are required. This cost both money and time, which in turn is more money.

Hence, Optic2Connect provides an elegant solution with our accurate modelling and simulation solutions, this accelerates manufacturing prototypes and at much lower production costs. Our software solutions provide a 10x improvement in time reduction and time to market. Further, our cloud solution overcomes traditional problems of insufficient servers / licenses, especially during periods of peak demand.

Metro450 Conference 2014 discusses all things 450mm wafers!

Thanks to the Enable450 newsletter, sent out by Malcolm Penn, CEO, Future Horizons, here is a piece on the Metro450 Conference 2014, held earlier this year in Israel.

Metro450 is an Israel-based consortium with the goal of helping the metrology companies advance in their fields. The consortium’s members include metrology and related companies, as well as academics who support these companies by performing basic research.

The conference was sponsored by the Israeli Chief Scientist Office, Applied Materials Israel and Intel. There were several goals for the conference: to provide an opportunity for industry leaders as well as academicians to meet and discuss the latest developments in the world of metrology, to present these advances to audiences which would normally not be privy to such information, and to learn more about the international effort in 450mm wafer technology.

Over 200 people attended this conference from Israeli companies and academia, as well as from Europe and the United States. Israeli companies included Applied Materials, Jordan Valley, Nova, KLA, Zeiss Israel, and others. Academic members included researchers from the leading Israeli universities, including the Technion, Tel-Aviv University. and Haifa University.

European companies were represented by ENIAC, as well as large corporations such as ASML as well SME-based companies. The G450C consortium, based in Albany, N.Y. was also well represented at this conference.

Some of the highlights of the conference included scientific discussions of different metrology methods, and their adjunct requirements, such as improved rapid wafer movement, improved sampling methods and fast computing. Presentations also included an overview of the advances necessary to move the industry forward, optical CD metrology, x-ray metrology, and novel piezo-based wafer movement.

A panel discussed various broad industry trends, including the timeline of 450mm wafers, European programs and the Israeli programs. International speakers discussed the European technology model, risk mitigation of 450 through collaborations, 450 collaborative projects under ENIAC, 450mm wafer movement challenges and metrology challenges beyond 14nm.

This second annual Metro450 conference took place this January at the Technion, Israel.

Renesas aims to increase its MCU share in India

Renesas Electronics recently opened its India subsidiary in Bangalore. Elaborating, Sunil Dhar, managing director of Renesas Electronics India said: "We are glad to announce the opening of Renesas Electronics India Pvt Ltd, a wholly-owned subsidiary of Renesas Electronics Singapore Pte Ltd., located in Bangalore.

"Since 2010, Renesas has been providing technical product support to its customers here via branch offices in Bangalore, Delhi and Mumbai. As part of its expansion plan, Renesas will turn our said branches into a full subsidiary.

"The branch office setup served us well when the organization was small and its role was limited. In order to expand further in terms of opening more offices in India for close customer support, and to be able to provide wider services to customers in India like reference software, hardware, reference solutions which would be developed in India, it would require us to have a permanent establishment here.

"Through this new company, we aim to expand business by providing the best solution offerings and technical support as well as a regional systems solution development expertise to the Indian market."

How does the India R&D team play a role in global innovation and where do you see Renesas Electronics in India five years from now?

He said that over 50 percent of the Renesas India team is application development or field engineers armed with knowledge of embedded hardware and software development and support.

In order to expand the footprint in Indian markets, Renesas plans to build up a strong application engineering team. India Application engineering team will engage with the Renesas headquarters, regional offices to develop new products and solutions dedicated for emerging countries, including India.

The application engineering team and the future solution centre aim to survey the market for solution needs, prepare India designed solutions fitting the price points and specifications points as required in the Indian market. Along with the customers, the team also intends to collaborate with the design houses to create innovative solutions addressing upcoming needs of the market. Our goal is to become the most trusted semiconductor solution provider in India.

What are the India-centric solutions that would be developed from the India Application Engineering team?

Dhar added that the needs of emerging markets are usually different in both specifications as well as price points. By providing dedicated local support via the new company, and with a focus on industrial and automotive applications for two- and four-wheelers, Renesas aims to increase its MCU share in India and expand its solution offerings with rich lineup of kit solutions (MCU + SoC + power devices) and platform reference boards (boards with complete ecosystem including devices and software) to provide customers a shorter time-to-market.

The team will initially focus on automotive and particularly, two-wheeler solutions. The intention is to expand the scope of the application engineering team’s activity to industrial and consumer appliances in near term.

What is the overall India employee strength? How are the investment plans looking up?

Dhar said: "In order to expand our footprint in Indian markets, we will double our headcount in near term.  Currently, we are just under 30 staff and over 50 percent of us are application development or field engineers armed with the knowledge of embedded hardware and software development and support. Upon setting up the organization in Sales and Marketing roles in the initial days, we also have plans to announce the setting up of a Solutions Centre in India to develop reference application solutions to enable our customers to use our devices.

"We are intending to invest in lab, infrastructure setup and expansion of activities in the next three to five years. Additionally, we are also considering investing towards 3rd party and IDH for enlarged business  engagement."

Trends driving automotive market in India
Regarding trends driving the automotive market in India, Dhar said that Renesas focusses on three business segments – automotive, industrial and home, OA and ICT. Renesas holds more than 40 percent global market share for automotive MCU business. Our target applications for automotive segment are automotive control and automotive infotainment and network.

Renesas has dedication applications solutions for integrated cockpit through system on chip, R-car ecosystem collaboration solution for e-mobility and automotive analog and power devices for driving, steering and braking.

As semiconductor technologies evolved, it has enabled automakers to integrate multiple applications on a single chip significantly reducing the board area; thus optimizing performance and adding new features for comfort, safety and infotainment. Power technologies have brought energy efficiency, limiting power consumption in vehicles. Advancements in process technologies will continue to drive the auto industry in the coming years.

Renesas, for instance, developed the industry's first 28nm flash memory IP for MCUs and the first semiconductor supplier to move from 40nm to 28nm process technology.

"Trends driving auto industry in India and globally are more of less the same. However, for India market, we see a specific demand for two-wheeler solutions and that is our target in coming years," he concluded.

Lastly, I must take the opportunity to thank Ms Shweta Dhadiwal-Baid and Ms Sharmita Mandal for making this happen! ;)

Set up strong methodology teams to create better verification infrastructure: Synopsys

This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as:

* Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution.

* No or very low investment in building better verification environments (based on best/new methodologies and best practices); instead maintaining older verification environments.

* Compromising on verification completeness because of tape out pressures and time-to-market considerations.

Would you agree that many companies STILL do not know how to verify a chip?

It could be true for smaller companies or start-ups, but most of the major semiconductor design engineers know about the better approaches/methodologies to verify their chips. However, they may not be investing in implementing the new methodologies for multiple reasons and may instead continue to follow the traditional flows.

How are companies trying to address those? One way to address these mistakes would be to set up strong methodology teams to create a better verification infrastructure for future chips. However, few companies are doing this.

Are companies realizing this and building an infrastructure that gets you business advantage? According to him, some companies do realize this and are investing in building a better infrastructure (in terms of better methodology and flows) for verification.

When should good verification start -- after design; as you are designing and architecting your design environment?

He said that good verification starts as soon as we start designing and architecting the design. Verification leads should start discussing the verification environment components with the lead architect and also start writing the verification plan.

Are folks mistaking by looking at tools and not at the verification process itself? He noted that tools play a major role in the effectiveness of any verification process, but we still see a lot of scope in methodology improvements beyond the tools.

What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities? As per Ghosh, there is not a single full-proof recipe for a ‘right’ verification path. It depends on multiple factors, including whether the design is a new product or derivative, the design application etc. But yes, it is very important to do comprehensive verification planning before starting the verification process.

How is Synopsys addressing this? Synopsys is said to be building a comprehensive, unified and integrated verification environment is required for today’s revolutionary SoCs and would offer a fundamental shift forward in productivity, performance, capacity and functionality.

Synopsys’ Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.

Verification Compiler includes:

* Better capacity and compile and runtime performance.
* Next-generation static and formal technology delivering performance improvement and the capacity to analyze a complete SoC (Property checking, LP, CDC, connectivity).
* Comprehensive low power verification solution.
* Verification planning and management.
* Next-generation verification IP and a deep integration between VIP and the simulation engine, which in turn can greatly improve productivity.  The constraint engine is tuned for optimal performance with its VIP library. It has integrated debug solutions for VIP so one can do protocol-level analysis and transaction-based analysis with the rest of the testbench.
* Support for industry standard verification methodologies.
* X-propagation simulation with both RTL and low power simulations.
* Common debug platform with better debug technology having new capabilities, tight integrations with simulation, emulation, testbench, transaction debug, power-aware debug , hw/sw debug, formal, VIP and coverage.

Top verification recommendations
What would be Synopsys' top five recommendations for verification?

* Spend a meaningful amount of time and effort on verification planning before execution.

* Continuously invest in building a better verification infrastructure and methodologies across the company for better productivity.

* Collaborate with EDA companies to develop, evaluate and deploy new technologies and flows, which can bring more productivity to verification processes.

* Nurture fresh talent through regular on and off-the-job trainings (on flows, methodologies, tools, technology).

* Conduct regular reviews of the completed verification projects with the goal of trying to improve the verification process after every tapeout through methodology enhancements.