Think AND not OR; Altera first @ 40nm FPGAs

Altera has announced two new product lines -- the Stratix IV FPGAs, which feature up to 680K logic elements, as well as the HardCopy IV ASICs, which has Gigabit transceivers embedded within the PLCs and allow seamless FPGA prototyping to hard core ASIC production.

Altera has also introduced the Quartus II software v8.0, which delivers unprecedented performance and productivity for FPGAs. It allows customers to assign power constraints on designs.

This is a global launch, and I feel proud to be associated with it. I am probably among the earliest to break this news to the world!

"All of these have been made possible due to Altera's relationship with TSMC," according to Gangatharan Gopal, country manager, India, Altera Semiconductor India Pvt. Ltd.

Altera's 40nm devices are targeted at high-end applications such as wireless and wireline communications, military, broadcasting and ASIC prototyping.

The Statix IV FPGAs feature 680K logic elements, up to 22.4Mbits internal RAM, up to 48 transceiver blocks operating at up to 8.5Gbps, core performance of 350MHz, and hard IP for PCI Express Gen 1 and Gen 2.

The Stratix IV FPGAs are available in two majpr product groups -- the GX devices or Gigabit Ethernet devices, which have up to 530K logic elements, and the E devices or enhanced Stratix IV, which support more memory per logic element. There are a total of eight devices per family.

The HardCopy ASICs IV feature seamless prototyping, so that customers can have the same RTL, same IP set and one tool, come with transceivers -- similar transceiver block as the Stratix IV, offer lowest risk and lowest total cost access to deep sub-micron ASIC benefits, and provde 50x low power than companion FPGAs.

The HardCopy IV features 13.3 million gates. Gopal said: "Altera has surpassed the average industry ASIC density. We are now offering 13.3 million gates with HardCopy IV. With this, we can now address 80 percent of the market requirements."

The HardCopy IV also comes in GX and E versions. Each version has six devices, supporting more memories and transceiver blocks.

Higher densities require higher levels of productivity
Altera's Quartus II software v8.0 is specifically addressing this market need. It is said to be leading in productivity for high-end FPGAs and HardCopy ASICs. Features include TimeQuest -- for timing analysis, Compilation Speed -- via incremental compilation, PowerPlay technology -- which allows power management; and SOPC Builder -- which facilitates system-level design.

Altera is addressing the issue of compile times at three fronts -- algorithms, multiprocessor support and incremental compile support. The Quartus II v8.0 is said to deliver 20 percent average annual compile time improvement.