Mentor’s Wally Rhines on EDA industry — II

Friends, this is a continuation of my conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Software-to-silicon verification
Today there’s a growing focus on software-to-silicon verification, encompassing a full range of challenges that also includes embedded software, system validation and integration testing. How true?

Certainly true! The problem of hardware/software codesign and co-verification has been around a long time but, until this decade, generated less than $50million of annual EDA revenue.

Rhines said: “This decade, the market has grown rapidly and companies like Mentor have experience accelerated revenue growth in both their ESL design environments and their embedded software development tools and technology. Emulation has grown increasingly popular to verify not only hardware but to test application/embedded software.

“And, embedded software development tools, technology, RTOS, protocol stacks and LINUX middleware have all become part of the electronic product developers design environment.”

EDA in modeling and photomask correction
How and where does EDA fit into the big picture, particularly in the areas of modeling and photomask correction?

According to Rhines, for photomask correction, the EDA industry is the only provider, with two large EDA companies providing more than 90 percent of the optical proximity correction revenue.

“EDA companies have changed over the last decade due to the growth of OPC and DFM. Wafer fabs have now become major customers. Specialists in optics have joined traditional electronic design specialists at EDA companies to create the key technologies. EDA companies are now leading the way in the development of new process technology as evidenced by the IBM/Mentor joint development program at 22nm, he added.

Keeping integration density area savings compelling
Some semiconductor design companies seem to be refraining from adopting the latest process technology as it doesn’t offer compelling performance or power advantages to warrant the additional design cost.

In this regard, for how long will the integration density area savings you get by going to new nodes remain compelling?

Rhines said that advancing to new manufacturing nodes will always be attractive for some applications. However, with every generation of technology, there are some applications that don’t justify the move, at least until the new technology matures.

“While power considerations once seemed likely to slow migrations to new technologies due to leakage considerations, the developers of those processes have found ways to overcome problems so that many of the most power-sensitive portable applications, like cell phones, have aggressively moved to 40nm and will be early users of 32/28nm.

“One of the issues to watch for is whether the new generations of technology reduce the cost per gate or per bit for the largest designs, assuming the additional silicon area can be used effectively. Thus far, cost has been reduced consistently with each technology node but, especially if we are forced to move to a new illumination source for photolithography, this could change.”

22nm and sub 22nm
What does EDA need to consider when looking at 22nm and sub 22nm?

Rhines said that rhere are lots of issues and opportunities for EDA at 22nm and below.

“For example, computational lithography will challenge the most advanced algorithms for optical processing. Growth of complexity for sub-22nm chips will drive adoption of advanced functional verification capabilities that are already available from EDA companies, like intelligent testbenches, emulation, coverage-based verification and ESL transaction-based verification.

“Most importantly, place and route challenges will include some restricted design rules, as well as integration of design rule checking and lithographic rules into the router.”

Impact of process technologies
Is there any chance that the number of different silicon process technologies will shrink to a maximum of three? If yes, how will that impact EDA?

Standardization of processes helps reduce cost and minimize modeling expense for new design kits. There will always be specialty processes for analog, RF, power and other applications. For digital CMOS, a low power and a high performance option at each node seems likely to continue.

“From an EDA perspective, it would be nice to reduce the number of different design kits required to support design tools at a given technology node but the growing complexity of the kits will more than offset any reduction in work required by efficiency in the growth of the number of processes,” he added.

Working with instrument vendors
EDA companies are now also working with instrument vendors to get high-performance, high-quality products to market. Where is it all headed?

As per Rhines, the co-operation continues to expand. Examples include EDA companies working with producers of test equipment, metrology equipment, lithographic equipment and other types of manufacturing equipment to assure that variability in manufacturing processes can be correctly modeled.

3-D implementation
Is a lack of EDA tools is a bottleneck for 3-D implementation? What are EDA companies doing about this?

EDA companies all have work in progress to revamp the backend tool flows for 3-D packaging and the use of thru-silicon vias (TSV’s). Today, most stacked die are memories and most of them still use wire bonding. Recently, there have been products introduced using TSVs.

There are lots of challenges, however, in mixed logic/memory stacks to handle thermal dissipation, signal propagation delays, placement of TSV’s, etc. We are still far from an economic transition to 3-D for most designs but the EDA industry needs to stay ahead of the opportunity.

Lack of common format?
Chip and package suppliers say there are excellent point solutions for design of the chip, package and board, but they are not integrated. The lack of a common format among different EDA suppliers is a significant barrier. What’s being done on this front by EDA companies?

Rhines said that system simulation is an area of significant investment, at least for Mentor. System simulation for the aerospace, automotive and telecom infrastructure companies starts with UML, Matlab or other high level languages.

“The ability to comprehend multiple input standards at the various levels of design has been a high priority and system level design today supports a wide variety of standard inputs, from C to SPICE to VHDL-AMS, Verilog, System Verilog and VHDL, to execute electronic and mechatronic simulations.

“Support of open standards is critical to the advancement of design technology and integrated design flows. Although there are EDA companies who may, from time to time, try to drive their own proprietary formats and models, I believe the support of open standards is the route to success for both the EDA industry and its customers.”

You gotta fight for your life in EDA!
As they say, “You gotta fight for your life in EDA!” How true, as far as the EDA industry is concerned?

Rhines noted: “EDA is a competitive industry with three very large competitors and more than five hundred small ones, not including the EDA design services companies. Despite the competition, the number of EDA companies grows each year with the addition of more startups more than offsetting the number of companies acquired or going out of business.

“There are significant economies of scale in R&D for EDA so a single company leads in each major product segment, e.g. logic synthesis, physical verification, place and route, PCB design, etc., by a large margin, averaging 70 percent market share.

“Only new capabilities generate revenue growth of the EDA market; established design methodologies produce about the same amount of license and maintenance revenue each year. While none of the established EDA product segments provides any substantial revenue growth for the EDA market, each requires increasing R&D spending to extend the capability to new technologies. That makes it a very difficult business for all but the leader in each product segment. That’s why multi-vendor flows continue to be the only competitive approach to design.”

Mentor India’s role
Lastly, I quizzed him on the achievements of Mentor Graphics India so far, this year.

Mentor Graphics India provides leading edge R&D and world-class application support for our customers’ design groups. Our two R&D centers are in Noida and Hyderabad, while our customer sales and support operation is based in Bangalore.

Mentor India R&D facilities assume complete development responsibilities for product families in functional verification, emulation, modeling, logic synthesis, physical verification and cabling and wire harnesses for automotive/aerospace applications.

“Recent contributions have been development of capabilities for hardware acceleration of test benches and tools to assist in the use of System Verilog OVM for verification. In the future, Mentor India will accelerate development of verification IP,” Rhines concluded.