Mentor’s Wally Rhines on global EDA industry and challenges

Thanks to Veeresh Shetty at Mentor Graphics, I was very fortunate to get into a conversation with Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., who was recently on a visit to India for the EDA Tech Forum as keynoter.

Besides discussing the global EDA industry, the challenges it is currently facing, we also discussed industry issues such as whether the lack of EDA tools is a bottleneck for 3-D implementation, EDA in the big picture, with regard to areas such as modelling and photomask correction, and so on.

State of global EDA industry
According to Walden Rhines, 2008 and the first quarter of 2009 are the weakest periods ever reported by the EDA industry.

He said: “A substantial portion of the weakness during this period was caused by a change in revenue recognition accounting by one of the major EDA companies. Before 2008, there had only been two years of negative EDA revenue growth in history and both of those were very minor negatives (i.e., almost zero) and both of those were caused primarily by changes in revenue recognition accounting, one each by each of two major EDA companies.”

While this recession is the most precipitous drop in electronics industry history, the normal pattern of preserving most R&D spending has been maintained by most electronics companies. As a result, the decline in EDA revenue is small when compared to the decline in semiconductor industry revenue.

“As the electronics industry recovers, and its R&D spending once again comes in line with its growing revenue, the EDA industry should recover as well. Positive signs include the strength of the semiconductor sequential revenue growth in Q209 and the fact that the Q109 rate of year to year decline in EDA revenue was nearly half the rate of decline of the fourth quarter of 2008,” he added.

Tech challenges
What would be the biggest technical challenges facing the EDA industry right now? Rhines said that the largest technical challenges for the EDA industry right now are:

1) low power design (from system level through physical layout),

2) keeping up with the growing functional verification challenge (by developing new approaches including ESL, coverage based verification, emulation, intelligent testbench, hardware acceleration of test benches, assertion-based verification, etc.) and

3) dealing with manufacturing variability (through application of design-for-manufacturing techniques to design).

The conversation continues in a while… I’ll be back!