FPGA Camp in Bangalore discusses various industry aspects

Today, FPGACentral hosted its first ever FPGA Camp in Bangalore. The conference mainly aimed at bringing the engineers together and discussed the various aspects of the FPGA, mainly next generation FPGA technology, application, methodology, best practices and challenges, etc.he morning session rolled out with a session on ‘Today’s FPGA Ecosystem,’ where the participants included, Neeraj Varma, country manager – Sales, India and Australia/NZ, Xilinx India, Wai Leng Cheong, regional sales manager, South Asia Pacific, Altera Singapore, and Rakesh Agarwal, country manager, India & ANZ, Lattice.

Adrian Hernandez, senior manager, Xilinx USA, gave a presentation on ‘Mastering FPGA Design through Debug.’ This was followed by John Wei, High Speed System Specialist, Altera, Hong Kong delivering a lecture on the ‘Trends and challenges in designing with high speed transceivers based FPGAs, and signal Integrity concerns.’ The morning session was wrapped up by Srinivasan Venkataramanan, CTO, CVC, who presented on ‘Upgrading to SystemVerilog for FPGA Designs.’

A highlight of the afternoon session was a panel discussion on ‘State of FPGA technology and its adoption in India.”

Now, I am not really posting anything specifically on the sessions as these were mainly targeted toward engineers, and I, for a change, decided to simply sit back and listen to the speakers, rather than take notes.

Just a few points from here and there. For instance, Lattice’s Rakesh Agarwal mentioned that the company’s mid-range ECP3 is the lowest power SerDes enable FPGA in the market. The company is focused on markets where it can differentiate with high value, low power solutions, and where it has the scale to effectively compete.

The single most important feature that one must keep in mind when designing and verifying FPGA based projects is device reconfiguration. Xilinx’s Adrian Hernandez suggested that users should build on the FPGA’s reconfiguration. He called upon them to share knowledge and experiences. One of the points raised by John Wei was that advanced oscillator and hybrid CDR enables 25Gbps at the 28nm CMOS process node in FPGAs.

SystemVerilog interfaces have quickly found way into new designs, as they are useful for RTL designers and verification engineers. Srinivasan Venkataramanan touched upon the ecsystem around the SV-FPGA, adding that all of the major EDA vendors support SystemVerilog for design.

On the event itself, Navin Kumar and his team, including the volunteers, deserve a huge round of applause for pulling off this event. It was the first of its kind in India, an open source conference — with free attendance, etc. I believe, more people turned up, than originally expected. The turnout itself was interesting, with a mix of engineers, students and of course, the industry.

There were some minor hiccups regarding the location/venue and the positioning of booths — some of which looked really cramped for space, etc. However, these are really very minor issues, which the FPGACentral India team is sure to address in its forthcoming events. Well done guys!