Monday, January 28, 2013

Global semiconductor industry to grow 7.9 percent in 2013

According to Malcolm Penn, CEO, Future Horizons, the outlook for the global semiconductor industry in 2013 is likely to be +7.9 percent. This means, the global semiconductor industry will likely grow to $315.4 billion in 2013.

Should this happen, it would be significant, given that this is the third year in a row that the market failed to break the $300 billion barrier. The global semiconductor clocked around $292.3 billion in 2012, as against $299.5 billion In 2011.

I asked Malcolm Penn the rationale behind this. He said, the rationale is exactly the same as that for 2012. There is said to be no change to last year's fundamental market analyses. That's not all! There are likely to be exactly the same (economic) downside risks as well.

The unit demand, capacity and ASPs are all 'positively aligned'. Here, it is advised that one should never underestimate the economy’s capacity to derail the chip market. Even the downside forecast has been to break the $300 billion barrier.

The global chip industry growth is driven by four factors. These are economy, which is on hold due to complete loss of confidence, unit demand, which is back on the 10 percent per annum treadmill (inventory gone), fab capacity, which is currently tight (very), especially at the leading technology edge, and ASPs, which are structurally following the usual ups and downs.

There is a very safe, long-term bet, provided companies execute properly. As it is, most firms don’t, as they are too pre-occupied with chasing short-term targets.

Finally, if 2013 shows a recovery, the global semiconductor market will likely go ballistic in 2014.

Thursday, January 24, 2013

Outlook for global telecom: 2013 year of LTE?

Stoke Inc. is an established player in LTE security, commercial  Wi-Fi and LTE enablement, and is already engaged research into small cell signaling issues. It will be displaying a range of solutions for the global telecom industry at the forthcoming Mobile World Congress 2013 in Barcelona, Spain.

Outlook for telecom in 2013
First, I asked Stoke about the outlook for the telecom industry in 2013. According to Dave Williams, CTO, Stoke, 2013 will be the year of LTE worldwide. Deployments will accelerate worldwide. Significantly, Europe, in particular, has woken up to LTE.

Next, large-scale infrastructure suppliers are experiencing shifts in demand.  While operators in the Americas and Japan are high spenders, in Europe there are major vendors whose technology posture is while newer players have become rising stars

Further, Wi-Fi as an ongoing force in the industry - with subscribers accustomed to ‘leaving’ their cellular providers for Wi-Fi options, operator services such as international roaming and rate plans are losing their money-spinning potential. 3G data plan revenues are shrinking because of the superior appeal of Wi-Fi to subscribers. Operators must accommodate this reality in their LTE planning.

As per Williams, a trend will be the polarization of the device landscape. The Android’s dream of many device manufacturers with one software interface has faded. We’re seeing a polarized landscape of Samsung/Google versus Apple. RIM is struggling and facing further potential challenges as many of its enterprise contracts approach end of life in 2013.  Microsoft may emerge as a player in in the tablet area.  Look for some M&A activity from unexpected areas as well. Also, small cells are seen as the answer to spectrum challenges, but the rollouts will be slow for the next two  years as the technology matures.

Finally, driven primarily by the popularity of Apple and Samsung personal devices, BYOD - Bring Your Own Device -  to work is a ground-up movement that has taken ID departments and security practitioners by surprise. This is likely to push regulatory measures – especially in the area of security - in the relatively near term. Access providers are under even more threat from the security perspective.

It is not all bad, though. For savvy operators, there is the prospect of providing trusted, high quality and easy connections to a large proportion of the estimated 7 billion BYOD users worldwide.

It would be interesting to hear about what are Stoke's plans for the MWC 2013. The official said, "At MWC, look for Stoke to announce its new generation LTE mobile border access gateway, new LTE signaling capabilities in its Security eXchange and, on the Wi-Fi eXchange side, a new event access offering in conjunction with an ecosystem of partners."

Stoke's Wi-Fi exchange gateway solution
Elaborating on Stoke's Wi-Fi exchange gateway solution, Williams said the Wi-Fi eXchange is a gateway application that automatically authenticates Wi-Fi attached subscribers and securely links them to their 3G or LTE cellular network services and/or to the Internet.

Wi-Fi eXchange enables the operators to maximize the benefits of service provider Wi-Fi while limiting traffic loads on the mobile core through dynamic, selective traffic steering. Wi-Fi eXchange is an important catalyst for operators seeking to transition from Wi-Fi as merely RAN congestion relief to Wi-Fi as a new service delivery medium.

On Jan. 23, Stoke announced the newly-available Wi-Fi eXchange gateway that is engaged in multiple commercial service trials uncovering new ways for telecommunications operators to incorporate Wi-Fi as a revenue-supporting service. In a single unit, Wi-Fi eXchange introduces a broad set of extremely flexible Wi-Fi management capabilities previously unavailable to mobile broadband carriers.

Wi-Fi Alliance has been instrumental in driving the evolution of Wi-Fi strategies, providing a forum for Wi-Fi operators, equipment providers and hardware manufacturers to develop industry-wide standards and programs which are critical to mass market adoption. The Passpoint certification program, launched in June 2012, has already seen significant industry adoption.

Wednesday, January 23, 2013

What's the impact on CMOS image sensors industry in 2013?

The CIS and camera module value chain in 2012 was ~$6.6 billion industry, of which ~$2 billion were from design overhead, selling, general and administrative, ~$3 billion from front-end, ~$0.4 billion from optical layers, ~$1.2 billion from BE/packaging, etc., according to Paul Danini, technology and market analyst, Yole Developpment, France.

There is also the camera module assembly and test segment. This segment has the integrated camera module suppliers,  and  the module assembly and test houses. The CMOS image sensor (CIS) shipments by market is set for a 11 percent CAGR growth from 2012-2017.
There was a $5.8 billion market in 2011 based on an estimated value of the first level packaged device. Samsung with 19 percent was the leader in 2011 revenue share, followed by Omnivision and Sony at 17 percent each, respectively, and Canon and Aptina Imaging at 10 percent each, respectively.

Samsung saw a 200 percent growth in smartphones. Omnivision had 50 percent growth from Apple iPad and iPhone4. Sony has grown with BSI CMOS in mobile phones. Canon pioneered CMOS in DSLR. Aptina Imaging is in high-performance specialty markets, and SETi and Galaxycore are gaining significant market share in Chinese mobile phone market.

There is a two-pronged approach to revenue growth and business strategy -- race to volume and market share with CAGR >15 percent, and profit enhancement strategy with single-digit growth.
Low price sensors are being offered by Galaxycore, Omnivision, SETi, and so on, while the likes of Sony, Samsung, etc. are plying innovative high-end sensors (>5MP).

A look at the manufacturing environment in 2012 shows 25 different CIS players and 40 separate CMOS image sensor lines globally. The 2011 CIS wafer production by region for 2.5M 8" eq. wspy was led by Japan at 31 percent, followed by Korea at 27 percent, Taiwan at 24 percent and Europe at 15 percent. From 2013 onward, Japan will maintain its lead while Taïwan and China will increase their share.

What's going to happen?
So what’s happening in the final markets? The keys to success are either Chinese and Taïwanese foundries, and simple designs or leading edge R&D such as 3D stacking, BSI, 3D imaging and high dynamic range.

And, what's the minimum requirement? It is 12-inch wafer production and backside illumination. These could be a necessity in the near future in the consumer market.

In the high-end applications, while emerging applications are boosting growth, the competition keeps getting stronger. So, what happens in the high-end market segments? There is an opportunity for CIS players that struggle in the mass consumer market, as the CCD to CMOS shift is accelerating at -16 percent CAGR of CCD sales.

Tuesday, January 22, 2013

Indian ESDM industry likely to grow 9.9 percent CAGR in 2011-15

The India Semiconductor Association (ISA), along with Frost and Sullivan released the 6th ISA-F&S Report on the India ESDM Market (2011-2015). Evidently, the focus is on electronics and semiconductors industries in India.

Only a few economies have exhibited the strength to weather the harsh conditions prevailing in the global environment. Such economies are especially remarkable since they are vulnerable to headwinds given the significant size of their GDP. India, despite its temporary slowdown in the last year, has not only withstood the adverse environment, but has also been witnessing green shoots of recovery.

The Electronics Systems Design and Manufacturing (ESDM) sector ranks high among the various segments that have contributed to creating this bulwark. The ESDM industry in India has continued to chart its journey northwards. While the industry may not have achieved the exponential growth forecast by experts, its performance in the last few years can be termed an achievement in view of the overall slowdown of the Indian economy.

The ESDM industry is expected to grow at a CAGR of 9.9 percent between 2011 and 2015 resulting in an industry size of $94.2 billion by 2015.
Although the electronics product market is growing a very fast pace, ironically most of the demand is being fulfilled by imports. The growth potential of the services component will be determined to a great extent by India’s ability to undertake higher value-add activities and cost competiveness.

Resolute focus on the ESDM industry and favorable policies to incentivize investment, adoption of new technologies, catalyzing innovation and entrepreneurship, enhancement of skills and addressing the disability cost of developing ESDM products domestically are the key ingredients to elevating India to a leading player in the global arena.

Key drivers and challenges for Indian ESDM industry
The positive factors far outweigh the challenges that impact the Indian ESDM industry. The growth of the product markets is one of the key drivers where mobile devices, consumer electronics and IT/OA products continue to script some of the high growth rates globally.

Financial inclusion programs and rising standards of living have generated demand for new products besides increasing customer-base of existing ones. India is also recognized globally as a key source of high technology skills which are leveraged by global corporations for generating value.

The global economic downturn has had a profound impact on the ESDM industry in the past quarters. This is expected to be temporary, and given the strong domestic growth potential, is expected to be overcome over the next two quarters. Our continuing reliance on imports is impeding growth of domestic manufacturing, which in turn is a major hurdle to the creation of a viable domestic ecosystem. The high cost of developing products including duties, taxation, capital and infrastructure are leading to a slow pace of investment in this sector.

In a developing economy like India, where the government is driving force through its role of policy maker and facilitator, new and evolving policies for ESDM are anticipated to spur the industry into a higher growth mode. The recognition of the ESDM industry as a key contributor to the GDP is a major step forward.

The national policies on telecom and electronics have the potential to bring about a major change in the domestic industry. Quick implementation of these policy initiatives will positively impact the development of the domestic product design and manufacturing industry.

The ESDM industry in India comprises of the following four key segments:
1. Electronic Products
2. Electronic Components
3. Semiconductor Design Services
4. Electronics Manufacturing Services (EMS)

The first two represents products, while the others highlight the manufacturing services and design services.

Saturday, January 19, 2013

Rolith’s rolling mask lithography cheaper, more scalable and flexible!

Rolith Inc., Pleasanton, California, USA-based nanotech disrupter, is developing advanced nanostructured coatings and devices based on a proprietary technology for high throughput, large surface area nanolithography.

Found in nature (moth eye, lotus leaf and others) and successfully replicated in research labs, these nanostructures have the ability to revolutionize architecture, lighting, consumer electronics, energy, data storage, life science, solar, and other industries. Rolith’s disruptive nanostructuring technology allows cost-effective scaling of nanostructures fabrication in conveyor and roll-to-roll modes.

Rolith, along with Asahi Glass Co. have recently partnered for anti-reflective glass.

Speaking about Rolith's rolling mask lithography, Dr. Boris Kobrin, president and CEO said that essentially, Rolith has come up with a new manufacturing method based on large area low cost optical lithography, usually used in semiconductor processing (processors, memory) in a silicon wafer form factor.

"Our process is much cheaper, more scalable and flexible, applicable for much larger substrates (architectural windows, solar panels, TV displays, etc.), but at the same time, reaching and even extending resolution (smallest feature sizes) of a traditional (and high cost) optical lithography."

How will this be better than other available solutions, especially those used in museums, galleries, etc?

According to Dr. Kobrin, currently, the used anti-reflective coatings are based on vacuum process (sputtering or 'physical vapor deposition' of solid metal oxide layers), pretty expensive process. Such sputtered layers add color to glass plates, have limited efficiency for wide range of colors (wavelengths) and for different angle of view.

"Our sub-wavelength (nanostructured) anti-reflective glass won't have additional materials (just glass), will have good efficiency for an entire visible spectrum and for angles of view up to 60 deg. Moreover, due to conveyor type of manufacturing process and scalable width of such conveyor, the process promises to be quite inexpensive (we have a goal eventually to get down to $2/m2)."

How is Rolith reducing or eliminating glare from passing through the lens? "We use the technique, which nature created for some insects (moth, for example), where nanostructured surfaces eliminate reflections and make objects invisible," he concluded.

Thursday, January 17, 2013

Synopsys on outlook for global semicon 2013!

Thanks to Sheryl Gulizia, senior manager, Worldwide Public Relations, Synopsys Inc., I was able to connect with John Chilton, senior VP of Marketing and Strategic Development, Synopsys. I discussed the global (and Indian) outlook for the semiconductor industry with him in detail.

According to Chilton, the semiconductor industry has repeatedly stared down the daunting technical challenges caused by the necessity of Moore’s Law and the inevitability of the laws of physics. Every time, the industry has risen to the challenge and delivered silicon that is smaller, faster and cheaper, and the design and systems companies that were quickest to exploit the new technologies reaped the great benefit.

Power dissipation challenging
One trend that has proven to be especially challenging is power dissipation. Although transistors get smaller, faster and cheaper, chip power keeps increasing.  Increasing power and decreasing size could have caused device-melting energy densities, but the industry rose to the challenge with more innovative physics along with smarter design methods and tools.

This time around, the challenge seems more fundamental, with the new nodes offering either better performance or lower power, but not both at the same time, and maybe not at a lower cost.
The fundamental driving factor behind innovation has been smaller, faster and cheaper transistors, with the cheaper part making the migration a no-brainer for everyone.  Unfortunately, this time the new node is not expected to be cheaper.

App processors to drive move to 20nm
Application processors for mobile and cloud-based services will drive the move to 20nm. These applications have the volume and power/performance needs to justify the expected investment required to embrace the 20nm node. Recent product announcements at CES underscore the emergence of the ‘cloud to mobile client’ trend in consumer electronics.

Dell and Wyse unveiled the project Ophelia. Ophelia is a USB memory stick-sized thin client that will plug into any compatible TV or Dell monitor. The device will boot into an Android OS and turn any TV into a portal to access a computer somewhere else. Ophelia works by taking advantage of the MHL protocol and works with any MHL-enabled display. Over 100-million MHL-compliant chipsets have already been shipped, so the opportunities for this type of interaction are growing.

MHL, along with established standards such as USB and HDMI or even future short-range wireless standards, will enable consumers to plug their cell phone into any monitor or TV and consume content via their phone on a larger, more satisfying display.

Coincidentally, on the same day, Samsung announced consumer displays that utilize voice and gesture recognition. These emerging technologies will begin to redefine the way we interact with the cloud. Instead of carrying a laptop, you may end up waving and talking to a TV. In a futuristic presentation, Lexus showed a prototype of a laser-scanning system that is small enough to be mounted on a grill and makes 3-D maps of  the environment surrounding  a car. This kind of embedded vision technology will make its way into more devices as processor performance increases.

Developing these complex systems and applications will require a robust verification solution. Chip designers already use complex and exhaustive test benches to test individual blocks and subsystems. Verification engineers will need to move up to the next level and handle the full verification of the SoC within a target system.

Verification of an integrated system will require an integrated verification solution that includes not just simulation but also acceleration, emulation and formal debug. A new, integrated verification platform should combine these existing discrete technologies to offer the productivity needed to realize complex systems with predictable, manageable schedules.

Delivering the hardware simultaneously with a working OS and development kit will require virtual prototypes, which will be used by software developers prior to the release of working hardware.

Tuesday, January 8, 2013

Analog Devices launches portable lab for electronic circuit design

Analog Devices, as part of its University Program, has launched a personal, affordable and portable lab for electronic circuit design in India at the 26th international conference on VLSI currently ongoing in Pune, India.

Somshubhro Pal Choudhury, MD, Analog Devices India Pvt Ltd said that miniaturization and portability are the key trends today. Desktops have given way to laptops, and then to smartphones and tablets. The expensive vital signs monitoring equipment in hospitals is giving way to more wearable miniaturized power sipping (and not guzzling) medical gadgets. So, it is natural that education and training for engineering students also start taking a similar route.

What is this personal lab?
What it means that the lab will fit in the palm of your hand and would enable students to learn analog and mixed signal design, anywhere and everywhere not limited by their expensive university/college lab setup where access is fairly limited and the amount of time is limited as well to a few hours every week.
What does it mean for students?
With the lab, now, the students can carry on their experiments in their hostels/dorms and in their classrooms, using this portable lab, run experiments quickly during the class to see how real time real-life how a certain change in circuit impacts the results.

It has all the elements of a complete and expensive Lab setup on this portable kit connected with the student’s laptop. Students would not need equipment like oscilloscopes, waveform generators, logic analyzers and power supplies, expensive equipment that only top universities can afford.

Along with the portable kit, online and downloadable software and teaching materials, circuit simulation tools, online support and community, online textbook, reference designs and lab projects to design to enhance learning as a supplement to their core engineering curriculum are also provided free of charge.

This launch is likely to revolutionize electronic circuit design education and learning among the engineering academic community.

Monday, January 7, 2013

Focus on good power-aware verification strategy for SoCs: Dr. Wally Rhines

It is always a pleasure to chat with Dr. Wally (Walden C.) Rhines, chairman and CEO, of Mentor Graphics. I chatted with him, trying to understand gigascale design, verification trends, strategy for power-aware verification, SERDES design challenges, migrating to 3D FinFET transistors, and Moore's Law getting to be "Moore Stress"!

Chip design in gigascale, hertz, complex
First, I asked him to elaborate on how implementation of chip design will evolve, with respect to gigascale design, gigahertz and gigacomplex geometries.

He said: "Thanks to close co-operation among members of the foundry ecosystem, as well as cooperation between IDMs and their suppliers, serious development of design methods and software tools is running two to three generations ahead of volume manufacturing capability. For most applications, “Gigascale” power dissipation is a bigger challenge than managing the complexity but “system-level” power optimization tools will continue to allow rapid progress. Thermal analysis is becoming part of the designer’s toolkit."

Functional verification is continually challenged by complexity but there have been, and continue to be, many orders of magnitude improvement in performance just from adoption of emulation, intelligent test benches and formal methods so this will not be a major limitation.

The complexity of new physical design problems will, however, be very challenging. Design problems ranging from basic ESD analysis, made more complex due to multiple power domains, to EMI, electromigration and intra-die variability are now being addressed with new design approaches. Fortunately, programmable electrical rule checking is being widely adopted and will help to minimize the impact of these physical effects.

Is verification keeping up?
How is the innovation in verification keeping up with trends?

Dr. Rhines added that over the past decade, microprocessor clock speeds have leveled out at 3 to 4 GHz and server performance improvement has come mostly from multi-core architectures. Although some innovative approaches have allowed simulators to gain some advantage from multi-core architectures, the speed of simulators hasn’t kept up with the growing complexity of leading edge chips.

Emulators have more than made up the difference. Emulators offer more than four orders of magnitude faster performance than simulators and emulators do so at about 0.005X the cost per cycle of simulation. The cost of power per year is more than one third the cost of hardware in a large simulation farm today, while emulation offers a 12X savings in power per verification clock cycle. For those who design really complex chips, a combination of emulation and simulation, along with formal methods and intelligent test benches, has become standard.

At the block and subsystem level, high level synthesis is enabling the next move up in design and verification abstraction. Since verification complexity grows at about the square of component count, we have plenty of room to handle larger chips by taking advantage of the four orders of magnitude improvement through emulation plus another three or four orders of magnitude through formal verification techniques, two to three orders of magnitude from intelligent test benches and three orders of magnitude from higher levels of abstraction.

By applying multiple engines and multiple abstraction levels to the challenge of verifying chips, the pressure is on to integrate the flow. Easily transitioning and reusing verification efforts from every level—including tests and coverage models, from high level models to RTL and from simulation to emulation—is being enabled through more powerful and adaptable verification IP and high level, graph-based test specification capabilities. These are keys to driving verification reuse to match the level of design reuse.

Powerful verification management solutions enable the collection of coverage information from all engines and abstraction levels, tracking progress against functional specifications and verification plans. Combining verification cycle productivity growth from emulation, formal, simulation and intelligent testing with higher verification abstraction, re-use and process management provides a path forward to economically verifying even the largest, most complex chips on time and within budget.

Good power-aware verification strategy for SoCs
What should be a good power-aware verification strategy for SoCs

According to him, the most important guideline is to start power-aware design at the highest possible level of system description. The opportunity to reduce system power is typically an order of magnitude greater at the system level than at the RTL level. For most chips today, that means at least the transaction level when the design is still described in C++ or SystemC.

Significant experience and effort should then be invested at the RTL level using synthesis and UPF-enabled simulation. Verification solutions typically automate the generation of correctness checks for power-control sequences and power-state coverage metrics. As SoC power is typically managed by software, the value of a hardware/software co-verification and co-debug solution in simulation and emulation becomes apparent in power-management verification at this level.

As designers proceed to the gate and transistor level, accuracy of power estimation improves. That is why gate level analysis and verification of the fully implemented power management architecture is important. Finally, at the physical layout, designers traditionally were stuck with whatever power budget was passed down to them. Now,they increasingly have power goals that can be achieved using dozens of physical design techniques that are built into the place and route tools.

Friday, January 4, 2013

Ph.D candidates in VLSI industry! Is enough being done?

“Fine art is that in which the hand, the head, and the heart of man go together.” – John Ruskin.

“Great men’s honor ought always to be measured by the methods they made use of in attaining it.” – François Duc De La Rochefoucauld.

The 26th International Conference on VLSI Design 2013 is starting tomorrow at Hyatt Regency, Pune. Over the years, it has served as a forum for VLSI folks to discuss topics related to VLSI design, EDA, embedded systems, etc. The theme for the VLSI and embedded systems conference is green technology.

That brings me to a point raised by one reader of this blog- what’s the future of  Ph.D candidates in the VLSI industry! First, do not believe when you are told that you can only join academics in case you are a Ph.D. You can certainly switch over to R&D at the various VLSI companies! Or, you can start on your own, by developing something noteworthy!!

As for the current scenario, especially in India, students, or well, Ph.D holders should seriously consider developing useful projects for  use in India, and globally. It seems all too very easy for folks to join some large MNC in India or overseas, as according to such people: their jobs are done!

For some strange reason, semiconductor/VLSI development seems to have remained in the backburner in India! I was surprised on visiting a center in Bangalore to find students – actually, some Ph.D. holders – working on projects that may never even see the light of the day! That leads to the question: are the tutors guiding them enough? Do we even have systems in place that backs development?

Having spent a long time in the Far East, I have seen young Chinese and Taiwanese, Korean and Japanese men and women take to VLSI earnestly. How did they manage to do that? Mainly, by starting their own companies and developing some product!

Now, this is something not yet evident in India! Has anyone else asked this question? And, can the Indian VLSI community make this happen? It should not be very difficult, if the head, hand and heart are there in the deed!

As John Ruskin says, “Fine art is that in which the hand, the head, and the heart of man go together.”

François Duc De La Rochefoucauld. says, “Great men’s honor ought always to be measured by the methods they made use of in attaining it.”

Hope these words make sense! Developing and designing solutions is a fine art where the hand, the head and the heart must be in sync. And, if you have really developed a solution or a product, what were the methods you used to attain that! Answering these two questions are tough, but the answers really lie within us!

My question remains: do students (in India) really spend time for developing projects, or do they simply copy or buy projects?

Coming back to the VLSI conference, this year’s program will play host to the 4th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) as well. There will be discussions around topics such as design-for-test, fault-tolerant micro architecture, low power test, reliability of CMOS circuits, design for reliability, dependability and verifiability, etc.

A semiconductor company will likely be introducing a portable and affordable analog design kit. Students will no longer be required to go to expensive labs for developing projects. There should be lot of simulation tools, online course materials, community support, lab materials, etc. to use using the analog design kit. There should be a string of announcements too, so let’s wait for the event to start!

Tuesday, January 1, 2013

Outlook for electronics and semiconductors in 2013

Here is an outlook for electronics and semiconductors in 2013 by Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems (India) Pvt Ltd.

First, the past year, 2012, in review.

Globally, 2012 has been a challenging year for the semiconductor industry with the economic slump in Europe and the US. However, the long term outlook remains positive, with Gartner reporting that the growth in the electronics and semiconductor industries will outpace world GDP growth till 2016.

In India, the ambiguity around the telecom market, traditionally the biggest consumer of semiconductor equipment, was the main handicap to growth. On the positive side, the passing of the National Policy on Electronics (NPE) in 2012 promises a much-needed fillip to the electronics ecosystem. In 2013 we expect to see a positive impact in terms of home-grown electronics thanks to the provisions of the Policy.

Worldwide technology trends in 2013
User experience is the driving force behind many of the semiconductor design trends that we will see in 2013 and beyond. Consumers are demanding devices on which games, music, cameras, internet, and other apps all run simultaneously and seamlessly. As a result, mobility, application-driven design, video, cloud and security, all of which enable an enhanced user experience, are the drivers of the electronics and semiconductor world today.

Mobility is the single biggest driver for the semiconductor industry. The pervasiveness of mobility does not only affect the telecommunications industry, but also entertainment, home electronics, automotive and medical electronics.

For example, cutting edge mobile solutions in the healthcare field include devices that can monitor blood pressure and blood sugar levels remotely, and then transmit the readings to the physician for diagnosis and treatment; in the automotive sector, in-vehicle infotainment is expected to be the next big thing and end-consumers can look forward to real-time traffic reports, weather information, and entertainment options from next-generation cars.

Mobility has fundamentally altered how we produce and consume information. In the future, we can expect that devices will go one step further and actually interact intelligently with the user – we see the first steps of that with Apple’s Siri software.

Mobility has also created a completely new market for applications that enable a more interactive and satisfying user experience. It is via applications that system companies differentiate themselves and stand apart from the competition. The need to have applications on all kinds of devices is posing unique challenges to the semiconductor and EDA companies.

Whereas traditionally the hardware (silicon) was built first and then the software was added later, now developing the software and designing the hardware are becoming a parallel process. This gives rise to new EDA technologies that enable early software development using software models of system hardware long before silicon is ready. We will see this new way of designing continue to be a challenge going into 2013.

Per reports from Cisco, video will soon drive more than 90 percent of all global traffic on the Internet. As more and more entertainment and collaboration tools are launched, bandwidth-hungry video traffic will drive growth both in the end consumer market (mobile platforms) and the enterprise space (networking industry).

The cloud is closely intertwined with the growth in mobility – it is the cloud of network servers and backbone equipment that deliver the content and value to all mobile devices. For every 600 smart phones and every 120 tablets, one dedicated server is needed. With the demand for mobiles showing accelerated growth, the need for cloud computing technologies will be another key driver for the semiconductor industry.

Security underpins our information age. The vast amount of data residing in mobile platforms and cloud architectures is extremely vulnerable. As we move into 2013, we foresee a sharper focus on securing data and critical infrastructure from theft and hacker attacks.