Sunday, December 29, 2013

What does it take to create Silicon Valley!

I was pointed out to a piece of news on TV, where a ruling chief minister of an Indian state apparently announced that he could make a particular state of India another Silicon Valley! Interesting!!

First, what’s the secret behind Silicon Valley? Well, I am not even qualified enough to state that! However, all I can say is: it is probably a desire to do something very different, and to make the world a better place – that’s possibly the biggest driver in all the entrepreneurs that have come to and out of Silicon Valley in the USA.

If you looked up Wikipedia, it says that the term Silicon Valley originally referred to the region’s large number of silicon chip innovators and manufacturers, but eventually, came to refer to all high-tech businesses in the area, and is now generally used as a metonym for the American high-technology sector.

So, where exactly is India’s high-tech sector? How many Indian state governments have even tried to foster such a sector? Ok, even if the state governments tried to foster, where are the entrepreneurs? Ok, an even easier one: how many school dropouts from India or even smal-time entrepreneurs have even made a foray into high-tech?

Right, so where are the silicon chip innovators from India? Sorry, I dd not even hear a word that you said? Can you speak out a little louder? It seems there are none! Rather, there has been very little to no development in India, barring the work that is done by the MNCs.

One friend told me that Bangalore is a place that can be Silicon Valley. Really? How?? With the presence of MNCs, he said! Well, Silicon Valley in the US does not have MNCs from other countries, are there? Let’s see! Some companies with bases in Silicon Valley, listed on Wikipedia, include Adobe, AMD, Apple, Applied Materials, Cisco, Facebook, Google, HP, Intel, Juniper, KLA-Tencor, LSI, Marvell, Maxim, Nvidia, SanDisk, Xilinx, etc.

Now, most of these firms have setups in Bangalore, but isn’t that part of the companies’ expansion plans? Also, I have emails and requests from a whole lot of youngsters asking me: ‘Sir, please advice me which company should I join?’ Very, very few have asked me: ‘Sir, I have this idea. Is it worth exploring?’

Let’s face the truth. We, as a nation, so far, have not been one to take up challenges and do something new. The ones who do, or are inclined to do so, are working in one of the many MNCs – either in India or overseas.

So, how many budding entrepreneurs are there in India, who are willing to take the risk and plunge into serious R&D?

It really takes a lot to even conceive a Silicon Valley. It takes people of great vision to build something of a Silicon Valley, and not the presence of MNCs.

Just look at Hsinchu, in Taiwan, or even Shenzhen, in China. Specifically, look up Shenzhen Hi-Tech Industrial Park and the Hsinchu Science Park to get some ideas.

Sunday, December 22, 2013

How's the global semiconductor industry performing in sub-20nm era?

Early this month, I hobbled along to catch up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.

First, let's see how's the global semiconductor industry performing after entering the sub-20nm era.

Ahuja replied: "Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.

"At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors."

When speaking of advanced nodes, let's also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.

Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.

The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.

Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity Solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.

Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology.

Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.

FinFETs to 20nm - are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?

Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.

Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM's FinFET process technology.

Wednesday, December 11, 2013

Xilinx announces 20nm All Programmable UltraSCALE portfolio

Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.

Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.

“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”

Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.

* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.

* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.

KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.

There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.

Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”

The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.

There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite. UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.

Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.

Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.

“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”

The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.

UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.

Friday, December 6, 2013

Dr. Wally Rhines: Watch out 14/16nm technologies in 2014!

It is always a pleasure speaking with Dr. Wally Rhines, chairman and CEO, Mentor Graphics Corp. The last time I met him was at Santa Cruz, USA, during a global electronics forum in April this year.

Outlook for global semicon in 2014
Dr. Rhines said: "The outlook for the global semicon industry in 2014 is modestly positive. Most analysts will see single digiit growth. In memory, we have short supply vs. demand. While we had consolidation of the wireless industry, we still have volumes of handsets, tablets, etc. In the US, tablets are said to be the biggest growth area during Xmas.

"When you look at any product, you look at what more can it do. You look at more and more features that can be added. We have specialization in ARM-based chips. There are enough change dynamics that show demand.

"The iPad bridged the gap between the portable PC and phone. The infrastructure of apps has now made a huge infrastructure. If you are dependant on apps, there can be a differentiator.

"Wearable electronics is another great opportunity. However, it is still a small market. The electronic watch is interesting. We are in an era where there are some things that are key, and some require figuring out.

"There will be more and more need for specific devices, rather than only applications in future. The same thing was with the PC, which went from custom to specific needs."

In that case, how is the global semiconductor industry performing having entering the sub 20nm era?

He said that 2014 is going to be a big year. There will be releases of 14/16nm technologies. This will be the year when customers will be doing tests. There are companies in all regions of the world that will be doing such stuff.

Have FinFETs gone to 20nm? Are those looking for power reduction now benefiting?

Dr. Rhines said: "The big advantage is leakage. FinFET dramatically impacts current leakage. Now, attention will shift to dynamic power. It will once again be predominantly the consumer of power in large chips."

Outlook for EDA
Now, let's see what's the outlook for the global EDA industry in 2014.

Dr. Rhines said: "Whenever you create new technologies, you will need EDA. So, EDA will grow. New designs will also need EDA. There will be new EDA tools. EDA is now addressing thermal and stress issues in verification and design. Caliber PERC is our main product here. The upgrades are good for EDA. There are new things they have to adopt, in these tools.

Let's talk about embedded. Mentor released the new version of Sourcery CodeBench. What does it stand to gain?

Raghu Panicker, sales director, Mentor Graphics India said the Sourcery CodeBench is a real-time operating system (RTOS). That product is gaining momentum. Large MNC customers like Qualcomm are adopting this. Among small firms, there are medical, energy meter companies that are handling it as well.

Dr. Rhines added that Sorcery CodeBench is indicative of a trend - it is very open source based. It is now 20,000 downloads a month, so that is a big community.

Next is there any scope for the growth of biomems and optical telecom industry?

He said that both areas are interesting. Biomems are still a fairly small market. It is going to be evolutionary. As for optical telecom, over the last year or two, all participants have gone into a silent mode. Mentor is working with a number of customers.

Five trends to rule in 2014
Now, it was quiz time. First, the top five trends in the EDA industry during 2014. Dr. Rhines said:
* Growth of emulation for verification. The market is growing at over CAGR of 25 percent. Emulation is really big. It will be a big game changer for EDA.
* 16/14nm.
* Continued pressure on power as we go to FinFETs.
* Power reduction.
* Yield analysis for 14/16nm. A near range can be security.

Now, the top five trends for semiconductors in 2014! Dr. Rhines mentioned these as:
* Move to 14/16nm and cost.
* Growth in hybrid functions is another trend.
* Basic IoT.
* Security - how you verify designs.
* Continued commoditization of wireless applications.

Wednesday, December 4, 2013

Outlook 2014: Xilinx bets big on 28nm

We are in December, and its time for outlook 2014! First, I met up with Neeraj Varma, director-Sales, India, Xilinx. He said: "We expect the 28nm to do really well. From Apr. 13-Mar. 14, we expect revenues worth $250 milion from the 28nm line.

"We are now looking at the embedded market - and expect about $2 billion serviceable available market (SAM). We are looking at $8 billion SAM at the ASIC/ASSP displacement market, and of course $6 billion SAM for core PLD."

After a long time, Xilinx has been seeing positive capex. "We are entering a growth cycle for service providers and enterprises," he added.

A macro view of capex equipment spend is driven by LTE 27.2 percent at 2011-16, and optical networks 15.9 percent. The other areas include data center, enterprise switching and routing, and service provider switching and routing. Next, 3D ICs will enable Nx100G OTN, 400G OTN, MuxSAR, as well as top of the rack switch, I/O virtualization

Earlier, there were less than 50 ASICs start in communications in the top 10 OEMs. There were less than 20 28nm ASIC starts in at top 10 OEMs. As of 2012, less than 50 percent of the top 16 ASSPs vendors were losing money.

Customer needs are diverse now. Companies end up over designing a chip. People end up paying for what trey are not using.

Xilinx is offering the SMARTCORE IP for smarter networks and data centers. "40 percent of our wins have been achieved by integrating or displacing ASICs and ASSPs," he said. "We have 25 percent total wins across a broad set of apps/portfolio."

Some other gains for Xilinx:
* Xilinx gained 3 percent increase in PLDs.
* In wired and data centers, it has 12-percent CAGR from 2013-16.
* In wireless, it has 10-12 percent CAGR.
* In automotive smarter vision, it has 20 percent CAGR growth.
* In industrial, scientific and medical (ISM), it has 12 percent CAGR growth.
* In FY13E-FY16E, Xilinx expects to grow 8-12 percent, and has plans to increase the R&D revenue to 8.6 percent.

Thursday, November 28, 2013

Indian electronics scenario is still dull!

Leaptech Corp. was established to help the electronics and semiconductor manufacturing companies in India achieve global standards by adopting the latest technologies available worldwide. It represents the world’s leading companies offering automation equipment for PCB assembly, semiconductor, automotive and final assembly automation.

Suresh Nair, director, said that Leaptech is helping the electronics, semiconductor and automotive manufacturing companies in India by bringing in world class technologies from across the globe in assembly automation, the technologies, which are state-of-the-art.

"We provide both pre-sales and post-sales support to all the systems and solutions that we offer, complete post-sales support includes installation, commissioning, training, production support and process support through our factory trained engineers strategically located in Delhi, Mumbai, Bangalore and Chennai."

Leaptech provides audit and reconditioning services to enable customers improve productivity and uptime on their existing automated through hole and SMT assembly machines. Nair added: "We do provide audit and reconditioning services to customers where the machines were sold/supported by us. We may not be able to handle machines sold by other suppliers since that will be a breach of contract with out own principals."

As for the training on operational and maintenance aspects of through hole insertion and SMT machines, Leaptech also provide complete training on machines for operation, periodical maintenance, trouble shooting as well as preventive maintenance.

Leaptech offers consultancy services for new electronics setup as well as for new projects in the existing facility, which includes all detailing as well as knowhow on the process of assembly/production. our expert team is upto date with all latest trends in this industry.

Connected mobile devices
It will be interesting to get Leaptech's opinon regarding connected mobile devices. Nair said that connected mobile devices would grow for sure in the immediate future. Growth in the long term may depend on the contents of this segment and how interesting it is to the users.

With regard to automotive electronics driving energy efficiency, he added that Leaptech mostly sells automation equipment and the scope for these equipment toward energy efficiency for automotive sector is limited.

Indian electronics scenario in 2014 and beyond
According to Nair, the Indian electronics scenario is still dull and this may continue in the next year as well. Things could improve once the new manufacturing policy announced by the government starts seeing some investments.

To boost electronics manufacturing in India, it requires a simple action plan: make all finished electronics products imports more expensive and give incentives to local manufacturing.

However, he felt that nanotech will not emerge as a disruption in India, at least, not in the near future. It may make some impact in the long run.

Monday, November 18, 2013

Connecting intelligence today for connected world: ARM

ARM calls the spirit of innovation as collective intelligence at every level. It is within devices, between people, through tech and across the world. We are still pushing the boundaries of mobile devices today.

Speaking at the ARM Summit in Bangalore, Dr Mark Brass, corporate VP, Operations, ARM, said that the first challenge was the number of people on the planet. Technology development and innovation also pose challenges.

According to him, mobile phones are forecast to grow 7.3 percent in 2013 driven by 1 billion smartphones. Mobile data will ramp up 12 times between now and 2018. Mobile and connectivity are creating further innovation.

August, a compamy, has introduced an electronic lock for doors, controlled by the smartphone. Another one is Proteus, which looks at healthcare. The smartphone is becoming the center of our world. All sorts of sensors are also getting into smartphones. Next, mobile and connectivity are growing in automobiles. Companies like TomTom are competing with automobile companies. Connectivity is also transforming infrastructure and data centers. They are now building off the mobile experience.

As per ARM, an IoT survey done has revealed that 76 percent of companies are dealing with IoT. As more things own information, there will be much more data. The IoT runs on ARM.

"There's more going on than just what you think. IoT is not just about things. Skills development should not be an afterthought. Co-operation is critical. Solutions will emerge. All sorts of things are going to happen. Three years from now, only 4 percent of companies won't have IoT in the business at all," Dr. Brass added.

IoT will be present in industrial, especially motors, transportation, energy, and healthcare. Smart meters are coming in to help with energy management. There is a move to Big Data from Little Data.

Challenges in 2020 would be in transportation, energy, healthcare and education. ARM and the ARM partnership is addressing those. "We are delivering an unmatched diversity of solutions. We are scaling from sensors to servers, connecting our world," Dr. Brass concluded.

Thursday, November 14, 2013

India poses huge opportunity for DLP: TI

Texas Instruments has been a leader in DLP or digital light processing, a type of projector technology that uses a digital micromirror device. Kent Novak, senior VP, DLP Products, Texas Instruments (TI) mentioned that DLP became the no. 1 supplier of MEMS technology in 2004.

The DLP pico projectors business started in 2009. Now, pico is going into gaming systems, etc. In 2011, it went into the cinema industry. In India, out of 10,000 screens, close to 7,000 are now digital. In 2012, new DLP development kit was launched allowing developers to embed the DLP chip into non-traditional applications in new markets. In 2013, TI started working on DLP automotive chips.

He said: "DLP is an array of millions of digital micromirrors. We ship around 45 million devices. We see India as a growth opportunity for cimemas. In DLP front projection business, we have 60 percent share in India. Only 5 percent of Indian classrooms have projectors, making room for growth."

In low power pico projection, TI has 95 percent market share in India for standalone pico projection. A phone with pico projection was launched in India with iBall at 35 lumen.

DLP technology is available in India in:
Industrial: Machine vision can improve quality control in the Indian manufacturing sector.
Medical: Intelligent illumination systems for cost effective blood analysis.
Safety: Cost effective, accurate chemical analysis of food and industrial.
Automotive: Infotainment and safety solution being qualified.

DLP in automotive displays has several applications, such as wide field of view head up display (HUD) - app available by 2016, free shape interactive active console - app available by 2017, and smart headlights. Some other features include:

* High image quality: consistent contrast, brightness over lamp.
* Full, deep, accurate cover over lifetime.
* Easily enlarges larger display areas.
* High power efficiency.
* DLP technology automatically reduces reflection.

New market opportunities
There are said to be several new opportunities for DLP. These are in:

Industrial: Machine vision, spectroscopy, interactive display, 3D printing, intelligent lighting, digital light exposure.
Infotainment: Mobile phones, tablets, camcorders, laptops, mobile projection, ultra slim TVs.
Gaming: Dual console gaming, interactive gaming, near eye display.
Digital signage: Interactive surface, storefront interactive, retail engagement.
Automotive: Head up display, interactive display, intelligent lighting.
Medical: Spectroscopy, 3D printing, intelligent lighting.

TI has DLP LightCrafter family of evaluation modules. It enables faster development cycles for end equipment requiring smalll form factor, lower cost and intelligent, high-speed pattern display. The DLP LightCrafter 4500 features the 0.45 WXGA chipset. The DLP chip can enable new and innovative intelligent display apps. If your solution uses, programs or senses light, DLP could be a fit. DLP catalog offers programmable, ultra-high speed pattern. "DLP is light source agnostic. We use whatever's most efficient for brightness," he added.

Friday, November 1, 2013

SEMICON Europa 2013: Where does Europe stand in 450mm path?

SEMICON Europa was recently held in Dresden, Germany on Oct. 8-10, 2013. I am extremely grateful to Malcolm Penn, chairman and CEO, Future Horizons for sharing this with me.

SEMICON Europa included a supplier exhibition where quite a few 450mm wafers were on display. One highlight was a working 450mm FOUP load/unload mechanism, albeit from a Japanese manufacturer. These exhibits did illustrate though that 450mm is for real and no longer a paper exercise.

There was also a day-long conference dedicated to 450mm in the largest room. This was crowded throughout the time and a large number of papers were given.

Paul Farrar of G450C began with a presentation about Supply Chain Collaboration for 450mm. His key message was there are 25 different tools delivered to G450C of which 15 are installed in the NFN cleanroom. This number will grow to 42 onsite and 19 offsite by Q1 2015.

He stated that Nikon aims to have a working 193i litho machine in 2H 2014 and install one in Albany in 1H 2015. Farrar also reported a great improvement in wafer quality which now exceed the expected M76 specification, and prime wafers to the M1 spec should be available in Q3 2014. There has also been good progress on wafer reclaim and it is hoped some wafers can be reused up to 10 times, although at least three is the target.

Metrology seems to be one of the most advanced areas with eight different machines already operational. The number of 450mm wafers in their inventory now stands at over 10,000 with these moving between the partners more rapidly. It was immediately noticeable from Farrar's speech that G450C is now recognising the major contribution Europe is making to 450mm and is looking for more collaborations.

Facilities part of F450C
Peter Csatary of M&W then dealt with the facilities part of G450C, known as F450C. This group consists of:
• M&W (co-ordination)
• Edwards
• Swagelok
• Mega Fluid Systems
• Ovivo
• CH2MHILL
• Haws Corporation
• Air Liquide
• Ceres Technlogies
• CS Clean Systems

F450C is seen as streamlining communications with the semiconductor companies and their process tool suppliers. The group will focus on four key areas, namely Environmental Footprint, Facility Interface Requirements, Cost and Duration, and Safety and Sustainability.

One interesting point raised was that 450mm equipment is inherently more massive and one suggestion has been that ceiling mounted cranes will be required to install and remove equipment. This of course means that fab roofs would need to be stronger than previously. This topic was discussed at the latest F450C meeting subsequent to this conference.

Another new concept is that of a few standardised 3D templates and adapter plates to allow fab services to be pre-installed before the equipment is placed.

An interesting point made elsewhere by M&W is that the current preference is to place a fab where there are already other fabs in existence so that the infrastructure to transport products, materials and services is already in place, as are basic utilities such as power, natural gas and water supply.

However, the scale of the expected utility demand at 450 mm ups the stakes as for example a large 300 mm facility uses about 4 million gallons of water per day, whereas a 450 mm fab will use almost double that, putting immense strain on a location's infrastructure should there be other fabs in the region. This could affect future site selections.

An outcome of this phenomenon is that the reduction, reclaim and re-use of materials will no longer be driven only by the desire to be a good corporate citizen, but will also be driven by cost control and to ensure availability of required resources such as power, water, specialty gases and chemicals.

Wednesday, October 23, 2013

Intergence all about expertise in IT optimization!

Intergence is a consulting organisation specialising in network, application, and process optimisation. It provides consulting services to align IT to your business strategy; resourcing to provide highly skilled expertise and managed services to deliver challenging IT projects on time and to budget.

Utilising a unique combination of world class expertise, industry-leading methodology and unique tools, Intergence has a clear and common purpose – to allow clients to extract more value from their existing assets, whilst delivering a first-class service.

Peter Job, CEO, Intergence, said that Intergence is all about expertise in IT optimization. This is about extracting more value. “One key challenges we found was that we were on the second or third generation structure. It is about of our expertise. We operate on three areas – IT optimization, managed sourcing and managed services around managing applications.

“One of the challenges we are addressing are addressng the end user themselves. They have fast and quicker access to applications. We have launced two new products at Gitex – AppFire – allows you to look at the LAN and WAN and the application itself.

“The AppFlare – gives the ability to monitor applications running across the Internet. We place software agents and they report how apps are running.

“We also do lots of managed sourcing – building infrastructure. We are able to mobilise and get a team of experts to come and build the IT team and build the infrastructure. The third is infrastructure. We are looking at cloud, security, etc.

“We are from the UK, and our business is growing at 35 percent. We moved to Dubai in 2008.This is our fifth Gitex. It can be any medium- or large-enterprise, public sector organization.

“The geography is UK and Europe, as well as the GCC countries. We have plans to go to Africa in the future.

The expertise of Intergence is IT optimization. Enterprises can use the AppFlare to make their infrastructure run more efficiently.

This year’s show is the best according to Intergence. You are always going to see security issues. More people are offering cloud services.

Some trends in 2014 include:
* BYoD will become mainstream.
* IT departments will have to become business centers.
* As for the cloud market, by 2016, 60-70 percent of businesses will have hybrid cloud. Lot of companies are looking at software-defined networks.
* Cloud analytics will go up by two to three years. People can actually see their data, and take informed decisions.

Apple's done it again, wth iPad Air!

At San Francisco, Apple introduced the iPad Air that features a 9.7-inch Retina display in a new thinner and lighter design!

Earlier, yesterday, in India, Samsung announced the GALAXY Note 10.1! However, it isn't any match for the iPad Air!!

The release says that precision-engineered to weigh just one pound, the iPad Air is now 20 percent thinner and 28 percent lighter than the fourth generation iPad, and with a narrower bezel the borders of iPad Air are dramatically thinner-making content even more immersive.

Apple also introduced the new iPad mini featuring Retina display and 64-bit Apple-designed A7 chip.

The iPads feature two antennae to support Multiple-In-Multiple-Out (MIMO) technology, thus bringing twice the Wi-Fi performance to iPad Air and iPad mini with Retina display at a blazingly fast data rate up to 300 Mbps. The fact that Apple will be offering 128GB for both the models shows that it really means business!

Besides the iPad Air, there were some other announcements made by Apple. First, Apple introduced the next gen iWork and iLife apps for OS X, as well as the OS X Mavericks, which is now available free from Mac App store. Apple also introduced the all new Mac Pro!

And, what will it do to Apple's business? Well, there will definitely be many more buyers for sure. Gosh, what will I do? I have a third-gen iPad and this is a fifth-gen model! Never mind! All the best to those who would be buying the iPad Air! Brilliant!

DP Electronics aims to be best in power solutions

DP Electronics eK (Deutsche Power), based in Germany, with an office in Hong Kong, is showcasing power electronics products at Gitex 2013. It has assembling partners in Hong Kong, Hungary, China, Taiwan and Germany.

Helen Long, manager, International Affairs, said that the company’s mission is to be the best supplier of power solutions. The company will continue to tailor products for market needs, while maintaining high quality, integrated customer service and prompt delivery.

The cycle time for the development of new models of UPS has been rapidly shortening as the manufacturers take advantage of the latest advancements in the use of microprocessors (MPUs) and power semiconductor devices. Hence, the supplier’s products are also becoming lighter, smaller and increasingly intelligent, with a dramatic effect on cost reduction. DP Electronics’ range of UPS include over 60 models/ratings.

Some of its products include the DH series sine-wave inverter (1 KVA-2 KVA), suitable for small/medium home equipment, office and public devices, home lighting systems, fabrication and control systems, PCs, PoS devices, etc. The SOLO series simulated sine-wave inverters (1 KVA-2 KVA) is useful for tubelights, TVs. computers, stereos, PBXs, etc.

It is also offering solar panels (100W-300W), as well as off-grid and on-grid PV imverters with MPPT solar charger, and a PV charge controller. DP Electronics is also displaying optoelectronic LED lights for ceilings, corn ligts, warehouse lights, flood lights, spot lights and other lights of different concepts.

Among UPS, it is offering the XL Plus series line interactive UPS (650VA-3KVA), Elentra series line interactive sinewave UPS (1KVA-6KVA), Elektra series online high frequency UPS (1KVA-30KVA) and 1KVA~10KVA models. The Elektra series is available as online industrial grade UPS — 10KVA~60KVA models and 10KVA-3.5MVA models, respectively. Then, there is the Fuhrer series of modular online UPS from 10KVA~100KVA.

The supplier is also offering VRLA/SLA/GEL batteries in 2V/6V/12V types.

Monday, October 21, 2013

Odyssey offers ClearSkies SaaS cloud-based integrated security services

Odyssey Consultants is a PCI QSA, ISO 27001 certified infosecurity, infrastructure and risk management solutions integrator, and a managed security and outsourcing services provider. Founded 2002, it has since evolved into a regional leader in managed security and outsourcing services.

Odyssey’s range of solutions and services lie within a four-phase information security continuum, such as test and access, design and implement, monitor and respond, and outsourcing. According to the company, information security management involves the development, deployment, and ongoing monitoring and review of a combination of preventive, detective, and response processes and controls.

Odyssey is offering the ClearSkies security-as-a-service (SaaS) line of cloud-based integrated security services. ClearSkies platform has the necessary tools that enable the organizations reap benefits of the cloud without compromising on infosecurity.

The first of the ClearSkies series of services offered by Odyssey is the security information and event management (SIEM). SIEM provides organizations an adequate infrastructure in-house, with the opportunity to gain such capability in the cloud. ClearSkies is enriched with the vast know-how, expertise and intelligence of the latest threats and vulnerabilities that come right out of Odyssey’s Ithaca Labs. It transforms the service into a powerful information security tool for the client.

Odyssey also offers managed security and outsourcing (MSOS) services. Key benefits include:

* Enhanced 24/7/365 protection and monitoring of network, systems and security components.
* Continuous log analysis and correlation of events with real-time incident escalation.
* Focus internal resources on core organizational competencies.
* Threat analysis and access to security advisories issued by Ithaca Labs team.
* Minimized mean time to restore/recovery (MTTR) capability by proactive indentification of Internet threats.
* Retention of logs collected in a secure environment, helping clients meet regulatory compliance without needing to deploy costly and complex reporting tools and processes.
* Low TCO by eliminating the need to recruit, train and retain an in-house security capability.
* Notification of in-scope devices outage that impacts log collection.
* Access to MSOS secure portal for reviewing real-time alerts, published incidents and generate reports.

Odyssey has offices in Cyprus and Greece, and is exhibiting at the Gitex 2013 show in Dubai.

Sunday, October 20, 2013

Gitex 2013: All about Big Data and cloud

Its been warm and sunny in Dubai, UAE, host to the Gitex Technology Week 2013, at the Dubai World Trade Center. Opening today, the show is literally the live wire for the Middle East technology roadmap.

Well, it seems that this show is all about the Big Data and cloud. On Oct. 21st, there is the Cloud Confex, where enterprises can learn how they can achieve the benefits of transformation. Are the CIOs and the businesses really prepared for Big Data? You can find that out by attending the session on Big Data on Oct. 22nd. There is the digital strategies day as well, on Oct. 23rd, where enterprises can find out more about how to integrate mobile and social media into their business models. This session should help you understand what customers or users do online, and more importantly, why they do that!

There are said to be 1,500 or so exhibitors at Gitex 2013. My attention was drawn to the gsmExchange, said to be the global trading platform for mobile phone wholesale since 2000. You can buy or sell mobiles phones as well as refurbished mobile phones at this portal. You can also buy and sell mobile phone accessories as well. Kaspersky Lab has a large booth, catering to the Internet security and mobile security products. Cisco is showcasing its intelligent network  products portfolio.

Elsewhere, there’s news about Datawind, and its low-cost phablet for the Indian market at Rs. 6,999 (taxes extra). Cyberoam is showcasing the next generation firewall (NGFW) and its enterprise security offerings. TP-LINK has launched its flagship 802.11ac wireless router, which is providing up to 1750Mbps of wireless bandwidth and set to change the way we look at home networking.

Olivetti is presenting innovative solutions and products whose features will be of particular interest to banks and post offices, such as the revolutionary MB-2 ADF, an all-in-one product for bank front offices that combines specialised printer functions with those of an A4 scanner, a cheque reader and allows the automatic multi-page documents feed thanks to the ADF. It is also displaying the Oliscan A600, a duplex colour scanner, the M206 and M210 multiservice terminals, and so on.

I saw a booth from Dubai Silicon Oasis Authority (DSOA), which is showcasing the park’s hi-tech ecosystem. Five years ago, when I was in Dubai, the director had informed me that the DSOA was large enough to fit in eight wafer fabs! Where are those fabs, dear sirs? Does it seem that the focus has shifted from fabs to providing incentives and state-of-the-art infrastructure to technology companies looking to set up shop in Dubai? We will try and find out, time permitting.

There is a strong presence of the local government, with large booths showcasing their wares. The Dubai Smart Government has introduced several new applications, such as the mobile gateway app – mDubai, mPay app, HR self-service app, MyID and iProc mobile app, and the suggestions and complaints app. Great work!

There are large booths mostly, especially from Etisalat, the Middle East’s leading telecommunications operator and one of the largest corporations in the six Arab countries of the Gulf Co-operation Council, Intel, which is showcasing its enterprise solutions, and Huawei, which is targeting the data centers, as well as enterprises.

There will be more updates tomorrow, as I’ve to rush for a meeting.

Saturday, September 21, 2013

Spark’s back on Indian electronics!!

Well, well, well! Post the announcements by the Government of India last week of two 300mm fabs in India, this week, there have been a spate of announcements again! Here's what they are!

Yesterday evening, the Indian Cabinet Committee on Economic Affairs has approved setting up of Information Technology Investment Region (ITIR) near Hyderabad. Phase I will be from 2013 to 2018 and Phase II will be from 2018 to 2038.

The Government of Andhra Pradesh has delineated an area of 202 sq. kms. for the proposed ITIR in three clusters/ agglomerations viz.:

(i) Cyberabad Development Area and its surroundings,
(ii) Hyderabad Airport Development area and Maheshwaram in the south of Hyderabad, and
(iii) Uppal and Pocharam areas in eastern Hyderabad. The ITIR will be implemented in two phases.

Next, the Government of India finalized the setting up of a ‘Ultra-Mega Green Solar Power Project' in Rajasthan in the SSL (Sambhar Salts Ltd, a subsidiary of Hindustan Salts Ltd - a Central Public Sector Enterprise under the Department of Heavy Industry, Ministry of Heavy Industries & Public Enterprises) area close to Sambhar Lake, about 75 kms from Jaipur.

Further, India was recognized as ‘Authorizing Nation' under the international Common Criteria Recognition Arrangement (CCRA) to test and certify electronics and IT products with respect to cyber security. India has become the 17th nation to earn this recognition.

Then again, the ‘HTML 5.0 Tour in India' has now reached Hyderabad.

Also, India has offered to help Cuba develop its renewable energy resources. This has been conveyed to Marino Murillo, vice president of the Republic of Cuba at Havana, by Dr. Farooq Abdullah, Minister of New and Renewable Energy, during his trip to Cuba.

All of this is really brilliant stuff!

At least, I have never seen or heard about so much activity happening, especially in the electronics and solar PV sectors. One sincerely hopes that all of these initiatives will allow India to come to the forefront of the global electronics industry.

The spark seems to be coming back to the India electronics industry, after a very, very long wait! It is hoped that this stays on!!

Wednesday, September 18, 2013

ST intros STM32F4 series high-performance Cortex-M4 MCUs

STMicroelectronics has introduced the STM32F4 series STM32 F4x9 and STM32F401, which are high-performance Cortex-M4 MCUs.

On the growth drivers for GP MCUs, the market growth is driven by faster migration to 32 bit platform. ST has been the first to bring the ARM Cortex based solution, and now targets leadership position on 32bit MCUs. An overview of the STM32 portfolio indicates high-performance MCUs with DSP and FPU up to 608 CoreMark and up to180 MHz/225 DMIPS.

Features of the STM32F4 product lines, specifically, the STM32F429/439, include 180 MHz, 1 to 2-MB Flash and 256-KB SRAM. The low end STM32F401 has features such as 84 MHz, 128-KB to 256-KB Flash and 64-KB SRAM.


The STM32F401 provides the best balance in performance, power consumption, integration and cost. The STM32F429/439 is providing more resources, more performance and more features. There is close pin-to-pin and software compatibility within the STM32F4 series and STM32 platform.

The STM32 F429-F439 high-performance MCUs with DSP and FPU are:

• World’s highest performance Cortex-M MCU executing from Embedded Flash, Cortex-M4 core with FPU up to 180 MHz/225 DMIPS.
• High integration thanks to ST 90nm process (same platform as F2 serie): up to 2MB Flash/256kB SRAM.
• Advanced connectivity USB OTG, Ethernet, CAN, SDRAM interface, LCD TFT controller.
• Power efficiency, thanks to ST90nm process and voltage scaling.

In terms of providing more performance, the STM32F4, they provide up to 180 MHz/225 DMIPS with ART Accelerator, up to 608 CoreMark result, and ARM Cortex-M4 with floating-point unit (FPU).

The STM32F427/429 highlights include:
• 180 MHz/225 DMIPS.
• Dual bank Flash (in both 1-MB and 2-MB), 256kB SRAM.
• SDRAM Interface (up to 32-bit).
• LCD-TFT controller supporting up to SVGA (800x600).
• Better graphic with ST Chrom-ART Accelerator:
-- x2 more performance vs. CPU alone
-- Offloads the CPU for graphical data generation
* Raw data copy
* Pixel format conversion
* Image blending (image mixing with some transparency).
• 100 μA typ. in Stop mode.

Some real-life examples of the STM32F4 include the smart watch, where it is the main application controller or sensor hub, the smartphone, tablets and monitors, where it is the sensor hub for MEMS and optical touch, and the industrial/home automation panel, where it is the main application controller. These can also be used in Wi-Fi modules for the Internet of Things (IoT), such as appliances, door cameras, home thermostats, etc.

These offer outstanding dynamic power consumption thanks to ST 90nm process, as well as low leakage current made possible by advanced design technics and architecture (voltage scaling).

ST is making a large offering of evaluation boards and Discovery kits. The STM32F4 is also offering new firmware libraries. SEGGER and ST signed an agreement around the emWin graphical stack. The solution is called STemWin.

Sunday, September 15, 2013

Great, India’s having fabs! But, is the tech choice right?

The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:

Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.

Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.

Now, this is excellent news for everyone interested in the Indian semiconductor industry.

One look at the numbers above tell me - NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let's examine!

As you can probably see, both the projects have placed 22nm right at the very last phase! That's very interesting!

Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel's Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!

For discussion's sake, let's say, a fab in India comes up by say, early 2015. Let's assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn't it? Where will the rest of the global industry be by then?

You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members.

What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE's Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY's College of Nanoscale Science and Engineering!

So, what does all of this tell me?

One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space!  Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!

Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop right there!

Perhaps, these product lines will be good for India and serve well, for now, but not for long!

Saturday, September 14, 2013

Now, India to have two semicon fabs!

Finally, the Government of India has approved the establishment of a semiconductor wafer fab (fab) in India!

This is indeed heart warming news, especially for the Indian semiconductor and electronics industries. For years, India has been trying to get at least one fab up and running! Now, the dream is about to be realized!

Speaking from China, an ecstatic BV Naidu, chairman and managing director, Sagitaur Ventures, co-chairman, Karnataka ICT Grioup and former president, India Semiconductor Association (ISA) said: “This is really a fantastic news for the Indian semiconductor industry. The government has been trying to achieve this since 2008. The announcement goes as a strong signal to global community.”

Pradip Dutta, corporate VP and MD, Synopsys, said: “It is a momentous decision for the semiconductor industry and by extension the electronics industry for our country. It should lead to a level playing field for the local manufacturers and mitigate some of the disability factors. I sincerely hope the industry reacts positively to this news and this leads to a vibrant local IC design industry.”

Raghu Panicker, sales director, Mentor Graphics India, added: “For years, India has been trying to get at least one fab up and running! This has indeed been a long awaited news. Finally its not ONE, but TWO. The fabs would fuel the growth of semicon start up’s and electronics industry as a whole. It is a big step forward for the overall ESDM inititaive by IESA and government.”

Jaypee Group, IBM and Tower form one consortium. HSMC, STMicroelectronics and a Malaysian company are said to be part of the other consortium.

Sunday, September 1, 2013

Higher levels of abstraction growth area for EDA

San Jose, USA-based Atrenta's SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.


I started by asking how Atrenta provides early design analysis for logic designers? He said: "The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate 'predictions', without the time and cost required to actually send a design through detailed implementation."

There's a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.

Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.

How are SpyGlass and GenSys platforms helping the semiconductor industry? Dr. Ajoy Bose said: "SpyGlass is Atrenta’s platform for RTL Signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams. 

"GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done."

How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.

On another note, I asked him why Apple's choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.

Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: "We see strong growth.  Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry.  At a macro level, the consumer sector will drive a lot of the growth ahead.  For EDA, the higher levels of abstraction is where the growth will be."

Wednesday, August 28, 2013

Moore’s Law could come to an end within the next decade: POET

POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in ICs by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost.

POET's current IP portfolio includes more than 34 patents and seven pending. POET’s core principles have been in development by director and chief scientist, Dr. Geoff Taylor, and his team at the University of Connecticut for the past 18 years, and are now nearing readiness for commercialization opportunities. It recently managed to successfully integrate optics and electronics onto one monolithic chip.

Elaborating, Dr. Geoff Taylor, said: "POET stands for Planar Opto Electronic Technology. The POET platform is a patented semiconductor fabrication process, which provides integrated circuit devices containing both electronic and optical elements on a single chip. This has significant advantages over today’s solutions in terms of density, reliability and power, at a lower cost.

"POET removes the need for retooling, while providing lower costs, power savings and increased reliability. For example, an optoelectronic device using POET technology can achieve estimated cost savings back to the manufacturer of 80 percent compared to the hybrid silicon devices that are widely used today.

"The POET platform is a flexible one that can be applied to virtually any market, including memory, digital/mobile, sensor/laser and electro-optical, among many others. The platform uses two compounds – gallium and arsenide – that will allow semiconductor manufacturers to make microchips that are faster and more energy efficient than current silicon devices, and less expensive to produce.

"The core POET research and development team has spent more than 20 years on components of the platform, including 32 patents (and six patents pending)."

Moore's Law to end next decade?
Is silicon dead and how much more there is to Moore’s Law?

According to Dr. Taylor, POET Technologies’ view is that Moore’s Law could come to an end within the next decade, particularly as semiconductor companies have recently highlighted difficulties in transitioning to the next generation of chipsets, or can only see two to three generations ahead.

Transistor density and its impact on product cost has been the traditional guideline for advancing computer technology because density has been accomplished by device shrinkage translating to performance improvement. Moore’s Law begins to fail when performance improvement translates less and less to device shrinkage – and this is occurring now at an increasing rate.

He added: "For POET Technologies, however, the question to answer is not when Moore’s Law will end - but what next. Rather than focus on how many more years we can expect Moore’s Law to last – or pinpoint a specific stumbling block to achieving the next generation of chipsets, POET looks at the opportunities for new developments and solutions to continue advancements in computing.

"So, for POET Technologies, we’re focusing less on existing integrated circuit materials and processes and more towards a different track with significant future runway. Our platform is a patented semiconductor fabrication process, which concentrates on delivering increases in performance at lower cost – and meets ongoing consumer appetites for faster, smaller and more power efficient computing."

Friday, August 16, 2013

What’s happening with 450mm: G450C update and status

The Global 450mm Consortium (G450C) has been driving the effective industry 450mm development. It is co-ordinating test wafer capability supporting development and demonstrating unit process tool performance. The focus is now on improving tools with suppliers to be ready for customer operations.

Giving an update during the recently held Semicon West 2013 at San Francisco, USA, Paul Ferrer, GM, G450C, said that if one looks at the G450C lithography tool roadmap, by 1H-2014, the 300mm coupon, 450mm directed self-assembly and 450mm imprint will be completed. From 2H-2014 to 1H-2015, there will be 193i patterning service at Nikon’s site. Nikon 193i move-in will take place from 1H-2015 to 2H-2016.

Suppliers are developing the 450mm tool set with 10 tools per quarter being delivered to G450C, the global consortium for 450mm fabs. Significant progress has been made in wafer quality and wafer reclaim is almost ready. Automation and carriers are working, and suppliers are co-operating on the key initiatives. Global collaboration is said to be picking up steam.

In the NFX cleanroom, the 450mm OHT is ready for inter-fab transfer. There are nine tools in-fab — two metro, three process, and four stocker, respectively. There will be seven ODD 3Q2013, and 10 tools ODD 4Q2013, respectively.

As for 450mm notchless wafer activities, the key technical results include the backside fiducial marks that have achieved the desired accuracy (3σ = 0.5μm) using existing camera technology. There are design rules of fiducial marks, such as multiple locations (≤ 4) for robustness and speed, different patterns at multiple locations, and off crystal plane, fewer dots and shallower dots to minimize the Si crystal damage.

As for program highlights, there are collected designs from G450C member companies, tool suppliers, and optical detection suppliers. Also, there has been delivery of 300mm test wafers with fiducial marks. G450C has co-ordinated test wafer plans with suppliers. Further, for 450mm silicon wafer readiness, notchless wafers are technically achievable now.

The G450C members include CNSE/Research Foundation, GLOBALFOUNDRIES, Intel, IBM, Samsung and TSMC.

Thursday, August 15, 2013

300mm is the new 200mm!

300mm is the new 200mm, said GlobalFoundries' David Duke, during a presentation titled 'Used Equipment Market' at the recently held Semicon West 2013 in San Francisco, USA. Used semiconductor equipment sourcing and sales is a very interesting challenge.

Qimonda, Spansion, Powerchip and ProMOS jumpstarted the market. Now, there is a broadening user base. There is an unexpected uptake by analog and power device producers to achieve economies of scale. There has been legacy logic scaling. Also, the 200mm fabs are being upgraded to 300mm with used equipment. Many 300mm tools can “bridge” to 200mm easily.

Parts tools are seeding the ecosystem. Third parties are also able to support refurb as well as tool moves. However, we need more! Software licensing is becoming a smaller hurdle. There has been no over-supply yet!

So, what are the 'rough' rules of thumb for 300mm? First, there are approximately 1,500 individual tools in the open market. Few sellers know the values as the market is still developing. Twenty percent of the transactions drive 80 percent of sales. Today, the number of 300mm buyers is around  1/10th the number of 200mm buyers!

Lithography has been the biggest difference. Leading edge DRAM is far more expensive in lithography. Lithography has seen the most dramatic financial effects with explosive pricing in technology (immersion) and the need for capacity (two-three critical passes vs. one with dual/triple gate patterning. As of now, financial shocks and bankruptcies are the main drivers for used 300mm.

Next, 200mm is now the new 150mm! The 200mm OEM support is starting to dry up. It is nearly impossible to compete in productivity vs. 300mm. Oversupply is causing values to stay suppressed. The only bright spot being: there is still strong demand for complete fabs. The 200mm market split is roughly by 40 percent Asia and 60 percent rest of the world.

So, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV.

Friday, August 2, 2013

Welcome to the converged infrastructure!

Don’t want to miss deadlines? Feel challenged about resources to deliver on critical business issues/initiatives? Well, are you desirous of responding much, much faster to customer requirements? Welcome to the converged infrastructure (CI)!

Is the future of IT enterprises resting on a converged infrastructure? Perhaps, yes! The CI comes with pre-integrated storage, networking, and virtualization — all as a single platform. That would surely increase the efficiency, agility and resiliency of any organization.

So, what exactly does the CI involve? Well, it will integrate all your servers, networking and storage into a single solution. This would improve the utilization of these collective resources effectively and efficiently. There will be tremendous simplification and centralization of management of resources. Further, it can bring down your IT expenditure by at least 30-40 percent, if not more! Enterprises can even have their RoIs within one or two years of implementation.

Having a CI in an enterprise involves having a strategic approach that touches every part of IT, such as applications, infrastructure and management, leading to:

* Accelerated IT service deployment.
* Efficiency across the IT services lifecycle.
* Strengthened IT service quality.

Dell’s PowerEdge VRTX shared infrastructure platform aims to do exactly all of the above, thereby the redefine office IT! There are integrated servers, storage and networking in a compact chassis optimized for office environments.

Dell’s PowerEdge VRTX provides a shared infrastructure platform, scalable performance, flexible shared storage, simple and versatile systems management, integrated networking and flexible I/O, and seamless management integration. CIOs definitely do not need to worry about loud servers, cabling nightmares, etc.

Dell’s PowerEdge VRTX is meant not only for SMBs, but also for large companies in retail, banking, healthcare, education, financial, etc. For example, a large company may have a huge data center somewhere that manage various stores. However, at each individual store/location, there’s no central IT management or administration. Hence, this acts like an IT administrator-in-a-box by giving the IT administrator the ability to manage across any store/location across the world using just from one box.

The PowerEdge VRTX is really a shared infrastructure platform, offering extensive performance and capacity with office-level acoustics in a single, compact tower chassis. It is ideal for small and midsize businesses, as well as remote and branch offices of large enterprises.

There is no compromise on scalable performance. Dell VRTX can help businesses gain fast application response times, run multiple applications that need performance or low latency, power through peak processing periods and scale for future business growth. There is flexible shared storage. All four server nodes have access to the low-latency internal shared storage that is ideal for virtualization and clustering. Local storage is also available in the chassis, which is highly economical and easier to manage than traditional SAN.

The PowerEdge VRTX offers integrated networking and flexible I/O. It includes a GbE embedded switch that eliminates the need to purchase a separate networking device and PCIe resources that are shared across the compute nodes within the chassis.

It also allows simple, efficient and versatile systems management. Full-functioned unified system management with Chassis Management Controller (CMC) and GeoView helps take much of the time and effort out of system administration and control. Deploy, monitor, update and maintain through a unified console that covers servers, storage and networking. Dell’s VRTX systems management is also integrated with major third-party management tools, protecting the CIOs installed investments and allowing them to use what they know.

This is a paid post in conjunction with IDG and Dell.

Friday, July 19, 2013

Xilinx tapes-out first UltraScale ASIC-class programmable architecture

Xilinx Inc. has taped-out the first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture. It is said to be the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. Xilinx implemented the industry’s first ASIC-class programmable architecture called UltraScale.

These milestones expand on Xilinx’s industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite. Xilinx already has several firsts in the 28nm space, such as:

* First 28nm tape-out.
* First All Programmable SoC.
* First All Programmable 3D IC.
* First SoC-strength design suite.
Neeraj Varma, director-Sales, India, said that Xilinx’s global market share in the 28nm portfolio was 65 percent in March 2013. With the launch of the industry’s first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture, there are improvements such as 1.5-2x performance and integration, and a year ahead of the competition. It handles massive I/O bandwidth, massive memory bandwidth, massive data flow and routing, and fastest DSP processing. The architecture will scale — from monolithic to 3D IC, planar to FinFET, and ASIC-class performance.

The UltraSCALE architecture points to high performance smarter systems. For example, 1Tps in OTN networking, 8K in digital video, LTE-A in wireless communications, and digital array in radar. There will be requirements for massive packet processing over 400 Gbps wire-speed, massive data flow over 5Tbps, as well as massive I/O and memory bandwidth over 5Tbps, and DSP performance over 7 TMACs.

The mandate for ASIC-class programmable architecture is to remove bottlenecks for massive data flow and smart processing, high throughput with low latency, and efficient design closure with greater than 90 percent utilization without performance degradation. These are the benefits of applying leading edge ASIC techniques in a fully programmable architecture.

ASIC-like clocking maximizes performance margin for highest throughput. UltraSCALE ASIC-like clocking enables clock placement virtually anywhere on the die, making the clock skew problem go away. Also, highly optimized critical paths remove bottlenecks in DSP and packet processing. There is greatly enhanced DSP processing, high-speed memory cascading, and hardened IP for I/O intensive functions.

Next generation power management features also enable a leap in performance. The process node is up to 35 percent static at 20nm. There are more buffers for granular or coarse clock gating. Block RAM is dynamic power gating, hardened cascading. For transceivers, there are architectural optimizations. There is efficient packing and utilization of the logic fabric. For DSP, there are wider multipliers and fewer blocks per function. As for memory, there is DDR4, which operates at 1.2v vs.1.5v, voltage scaling.

The Xilinx KINTEX UltraSCALE will power 4×4 mixed-mode radios, 100G traffic manager NICs, super high-vision processing, 256-channel ultrasound and 48-channel T/R radar processing. The Xilinx VIRTEX UltraSCALE will power 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G muxponder and ASIC prototyping.

Xilinx worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The Xilinx Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in Q4-2013.

Wednesday, June 12, 2013

EC's goal: Reach 20 percent share in chip manufacturing by 2020!

The European Commission is said to have a goal: to reach 20 percent world-share in chip manufacturing by 2020! Heinz Kundert, president, SEMI Europe, has even laid out an industrial strategy that will cover three complementary lines, such as:

* Transition to 450mm, expected to primarily benefit equipment and material manufacturers in Europe.
* “More than Moore” on 200mm and 300 mm.
* “More Moore” for ultimate miniaturization on 300mm wafers.

Investment will be focusing on Europe’s clusters of excellence in manufacturing and design --- Grenoble, Dresden and Eindhoven-Leuven -- and support partnerships and alliances across the value chain in Europe.

The key question of why one needs 450mm wafers has been answered by Mike Bryant of Future Horizons. The European semiconductor industry’s vision is to recover a leading position in the world throughout the entire value chain and to reverse the current negative trend of its worldwide competitiveness.

Among the many strategies the EC is planning to adopt include:

* Benefit from a single explicit European semiconductor industry policy.
* Maintain a high level of R&D effort, in a balanced way between the 150/200/300/450mm fields, between “More Moore” and “More than Moore”.
* Strengthen all elements of the value chain, from design to application.
* Develop co-operating programs and synergy initiatives between all semiconductor actors operating in Europe.

Europe has always stressed on stronger co-operation among the other industry segments. Some of these are automotive, energy, healthcare and well-being, security and safety, etc.

Friday, May 31, 2013

Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines

Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute "Visionary Talk", he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?

Dr. Rhines said: "Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement."

Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?

According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.

He added: "Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.

"Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume."

Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?

"Yes, of course," Dr. Rhines said. "However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability."

What will be the impact of transistor variability and other physics issues?

As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.

Tuesday, May 28, 2013

Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence

Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.

The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.

At Cadence, the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence's focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.

What's going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year -- Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.

On the relationship between the electronics and the EDA industries, Ahuja said that the electronics industry was currently going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.

Friday, May 24, 2013

Cadence Tempus accelerates timing analysis and closure by weeks!

Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI).
Complexity is growing exponentially and signoff is the bottleneck. There is an increasing design complexity. Low power is important across markets -- from smartphones to datacenters. Time to market remains critical as well. Feature-rich devices are growing the design size.

Timing closure schedule and complexity have been increasing. In fact, up until now, timing closure solutions are said to have not kept pace with design complexity. The number of timing views are increasing with each new process node. The increased margins make timing closure very difficult. Exponential growth in design size and complexity are stretching the analysis capacity. Time in signoff closure has been increasing up to 40 percent of the design flow at 20nm.

Come Tempus!
The Tempus timing signoff solution is big on performance, accuracy and closure. For performance, it facilitates massively parallelized computation, is scalable to 100s of CPUs and there are optimized data structures. It allows up to 10X faster path-based analysis (PBA) and advanced process modeling for accuracy. Finally, for closure, it provides up to 10X reduction in closure time, is placement and routing aware and offers unlimited MMMC capacity.

Tempus offers an unprecedented performance, and handles 100s of millions of cells flat! It has an innovative hierarchical/incremental analysis. For design closure, the multi-mode, multi-corner (MMMC) is distributed or concurrent. There is physically aware optimization, such as graph- or path-based. The PBA is a detailed view of timing based on slew propagation.

With Tempus, Cadence is solving the design complexity challenge by eliminating the signoff bottleneck and enabling customers to meet their power, performance and time-to-market goals.

Tuesday, May 21, 2013

Semicon in sub-20nm era: Business as usual or different?

We are now entering the sub-20nm era. So, will it be business as usual or is it going to be different this time? With DAC 2013 around the corner, I met up with John Chilton, senior VP, Marketing and Strategic Development for Synopsys to find out more regarding the impact of new transistor structures on design and manufacturing, 450mm wafers and the impact of transistor variability.

Impact of new transistor structures on design and manufacturing
First, let us understand what will be the impact of new transistor structures on design and manufacturing.

Chilton said: "Most of the impact is really on the manufacturing end since they are effectively 3D transistors. Traditional lithography methods would not work for manufacturing the tall and thin fins where self-aligned double patterning steps are now required.

"Our broad, production-proven products have all been updated to handle the complexity of FinFETs from both the manufacturing and the designer’s end. From the design implementation perspective, the foundries’ and Synopsys’ goal is to provide a transparent adoption process where the methodology (from Metal 1 and above) remains essentially the same as that of previous nodes where products have been updated to handle the process complexity."

Given the scenario, will it be possible to introduce 450mm wafer handling and new lithography successfully?

According to Chilton: "This is a question best asked of the semiconductor manufacturers and equipment vendors. Our opinion is ‘very likely’." The semiconductor manufacturers, equipment vendors, and the EDA tool providers have a long history of introducing new technology successfully when the economics of deploying the technology is favorable.

The 300nm wafer deployment was quite complex, but was completed, for example. The introduction of double patterning at 20nm is another recent example in which manufacturers, equipment vendors and EDA companies work together to deploy a new technology.

Impact of transistor variability and other physics issues
Finally, what will be the impact of transistor variability and other physics issues going to be like?

Chilton said that as transistor scaling progresses into FinFET technologies and beyond, the variability of device behavior becomes more prominent. There are several sources of device variability.

Random doping fluctuations (RDF) are a result of the statistical nature of the position and the discreteness of the electrical charge of the dopant atoms. Whereas in past technologies the effect of the dopant atoms could be treated as a continuum of charge, FinFETs are so small that the charge distribution of the dopant atoms becomes ‘lumpy’ and variable from one transistor to the next.

With the introduction of metal gates in the advanced CMOS processes, random work function fluctuations arising from the formation of finite-sized metal grains with different lattice orientations have also become important. In this effect, each metal grain in the gate, whose crystalline orientation is random, interacts with the underlying gate dielectric and silicon in a different way, with the consequence that the channel electrons no longer see a uniform gate potential.

The other key sources of variability are due to the random location of traps and the etching and lithography processes which produce slightly different dimensions in critical shapes such as fin width and gate length.

"The impact of these variability sources is evident in the output characteristics of FinFETs and circuits, and the systematic analysis of these effects has become a priority for technology development and IP design teams alike," he added.

Monday, May 20, 2013

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. It offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys' IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it.

Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec's patented technology improves engineer's productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Speaking about IDesignSpec, Anupam Bakshi, founder, CEO and chairman, Agnisys, said: "IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible."

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

"IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the
user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models," added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: "It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions."