Tuesday, April 30, 2013

Why do we need 450mm wafers?

Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every eighteen months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield - this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation - this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes - this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus, at the 300mm transition, the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.

In addition, larger wafers and better yields allowed larger die sizes, which also reduced the cost of packaging and test, with wafer-scale integration once touted as a solution to reduce costs further at least for large systems. However, in recent years, the average die size has in fact shrunk and it is believed we are now around the optimal die sizes.

As mentioned above, some costs are not inherently reduced by a larger wafer size. Lithography costs are more or less proportional to the total area although small savings are still made as a smaller proportion of time is spent moving onto to the next wafer, whilst tasks such as metrology and CMP also increase somewhat with wafer size.

The result is that the cost of these types of operations grow as a percentage of the total cost of wafer processing and so in a following wafer size transition the savings made are on a smaller percentage of the overall processing cost. Thus, there comes a point where wafer processing costs are dominated by operations not effected by a wafer size increase and so increasing the wafer size becomes uneconomic.

Furthermore, although disputed by some companies, the International Technology Roadmap for Semiconductors (ITRS) has been predicting a slowdown in the rate of the technology cycle defined in Moore’s Law from two years to three years, resulting in a slowing of the increase in functional density per square centimetre.

At the same time the cost of wafer processing is predicted to grow far more rapidly than in the past due to the need to introduce new processes or processing techniques at every node. An interesting slide from ARM below paints a picture of this well. Obviously, it is not the actual new process names in the boxes that count so much as the fact there are so many of them.

Friday, April 26, 2013

Focusing light on breast cancer diagnostics

A team of scientists at the Massachusetts Institute of Technology (MIT), comprising principally of Dr. Ishan Barman, Dr. Narahara Chari Dingari and Dr. Jaqueline Soares, and their clinical collaborators at University Hospitals, Cleveland have developed the Raman scattering-based concomitant diagnosis of breast cancer lesions and related micro-calcifications.

Let’s find out more about this new breast cancer research done by the team at MIT.

Early detection necessary!
According to MIT, one in eight women in the US will suffer from breast cancer in her lifetime and breast cancer is the second leading cause of cancer death in women. Worldwide, breast cancer accounts for 22.9 percent of all cancers (excluding non-melanoma skin cancers) in women. In 2008, breast cancer caused 458,503 deaths worldwide (13.7 percent of cancer deaths in women).

Therefore, technological advancements for its early detection and subsequent treatment can make a significant impact by preventing patient morbidity and mortality and reducing healthcare costs, and are thus of utmost importance to society. Currently, mammography followed by stereotactic breast biopsy serves as the most promising route for screening and early detection of cancer lesions.

Nearly 1.6 million breast biopsies are performed and roughly 250,000 new breast cancers are diagnosed in the US each year. One of the most frequent reasons for breast biopsy is microcalcifications seen on screening mammography, the initial step in early detection of breast cancer. Microcalcifications are micron-scale deposits of calcium minerals in breast tissue that are considered one of the early mammographic signs of breast cancer and are, therefore, a target for stereotactic breast needle biopsy.

However, despite stereotactic guidance, needle biopsy fails to retrieve microcalcifications in one of five breast biopsy patients. In such cases, the resulting breast biopsies are either non-diagnostic or false-negative, thereby, placing the patient at risk and potentially necessitating a repeat biopsy, often as a surgical procedure.

There is an unmet clinical need for a tool to detect microcalcifications in real time and provide feedback to the radiologist during the stereotactic needle biopsy procedure as to whether the microcalcifications seen on mammography will be retrieved or the needle should be re-positioned, without the need to wait for a confirmatory specimen radiograph.

Such a tool could enable more efficient retrieval of microcalcifications, which would, in turn, minimize the number of x-rays and tissue cores required to achieve a diagnostic biopsy, shorten procedure time, reduce patient anxiety, distress and discomfort, prevent complications such as bleeding into the biopsy site seen after multiple biopsy passes and ultimately reduce the morbidity and mortality associated with non-diagnostic and false-negative biopsies and the need for follow up surgical biopsy.

If 200,000 repeat biopsies were avoided, at a cost of $5,000 per biopsy (a conservative estimate and would be much higher for surgical biopsies), a billion dollars per year can be saved by the US healthcare system. The MIT Laser Biomedical Research Center, has recently performed pioneering studies to address this need by proposing, developing and validating Raman and diffuse reflectance spectroscopy as powerful guidance tools, due to their ability to provide exquisite molecular information with minimal perturbation.

Specifics of the technique
Stating the specifics of the technique developed by MIT, the team said that their research focuses on the development of Raman spectroscopy as a clinical tool for the real time diagnosis of breast cancer at the patient bedside. “We report for the first time development of a novel Raman spectroscopy algorithm to simultaneously determine microcalcification status and diagnose the underlying breast lesion, in real time, during stereotactic breast core needle biopsy procedures.”

In this study, Raman spectra were obtained ex vivo from fresh stereotactic breast needle biopsies using a
compact clinical Raman system, modeled and analyzed using support vector machines to develop a single-step, Raman spectroscopy based diagnostic algorithm to distinguish normal breast tissue, fibrocystic change, fibroadenoma and breast cancer, with and without microcalcifications.

The developed decision algorithm exhibits a positive and negative predictive value of 100 percent and 96 percent, respectively, for the diagnosis of breast cancer with or without microcalcifications in the clinical dataset of nearly 50 patients.

Significantly, the majority of breast cancers diagnosed using this Raman algorithm are ductal carcinoma in situ (DCIS), the most common lesion associated with microcalcifications, which has classically presented considerable diagnostic challenges.

This study demonstrates the potential of Raman spectroscopy to provide real-time feedback to radiologists during stereotactic breast needle biopsy procedures, reducing non-diagnostic and false negative biopsies. Indeed, the proposed approach lends itself to facile assembly of a side-viewing probe that could be inserted into the central channel of the biopsy needle for intermittent acquisition of the spectra, which would, in turn, reveal whether or not the tissue to be biopsied contains the targeted microcalcifications.

Tuesday, April 23, 2013

Coto announces MEMS based magnetically operated switch

According to Stephen Day, VP of Technology, Coto Technology has the number 1 share in reed relays and relay products. The Coto brand is associated with the broadest portfolio, best in class quality, dedicated technical support, and a provider of innovative solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Coto has announced the RedRock, a new MEMS based magnetically operated switch. The RS-A-2515 is the world's smallest wafer level packaged magnetically operated reed switch. It consumes zero power, measures 2mm3 in footprint and switches at less than 0.3W. It delivers high reliability and surface mount package.

The small footprint means use of less PCB real estate, no operate power means a longer battery life. The low switching power leads to higher reliability. The high directionality leads to resistance to stray fields. Hot switchable feature leads to higher reliability.

Together, Coto has managed to combine the best of two worlds -- traditional reed switches with MEMS processing. There is high aspect ratio microfabrication (HARM). This is the first commercially available switch. It produces structures that generate strong contact closure forces. The forces are many times greater than the previous MEMS based magnetic switches. It also enables hot switching up to several hundred milliwatts.

HARM is the key to making it all possible. The benefits are many, from temperature rise vs. carry current, to RedRock contact life test, 1V 1 mA hot-switched load. RedRock allows for small size, zero power consumption and high power switching.

At the moment, Coto is leveraging RedRock into high growth applications. In the future, Coto will integrate sensor solution as well. RedRock's unique combination of features include reed -- no power and high current, and MEMS -- no power and small size, as well as GMR/Hall -- small size and high current -- to deliver the RedRock, which features no power, small size and high current.

Monday, April 22, 2013

Dr. Wally Rhines on fortunes of global semiconductor industry

It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.

Status of global EDA industry
First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: "The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months."

For the record, the Electronic Design Automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.

Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest - about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.

In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.

DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. "That's actually a little faster than how semiconductor R&D is growing," added Dr. Rhines.

Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: "The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry."

According to him, smartphones should see further growth. "There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years," he said. "A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit."

"A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen," he added.

Mentor and embedded
As for Mentor Graphics and embedded software and systems, Dr. Rhines said that embedded took off last year. With the Sourcery CodeBench, it is getting even more popular. Mentor Graphics will play a deeper role in embedded in future. It will be able to connect with a lot of India-based engineers who are already using the Sourcery CodeBench.

Embedded systems and software touches on industrial and other areas of telecom as well, along with analog, power and sensors, as they continue to become more intelligent.

Future areas of growth
Tablets are a growth market, especially, iPads. New products with added communications are evolving. There is also an amazing number of networking chips in design and production.

Analog is yet another area of growth. Hybrid chips, combining MEMS and ASIC is also a growth area. One other key growth area will be the stacked memory die. According to Dr. Rhines, dollar growth will be strong in memory next year.

Automotive is another strong segment. More and more automobiles are becoming mobile servers. Yet another growth area is the Internet of Things, followed by medical electronics. In the latter, implantable devices and hospital equipment are growing. As for skin-based electronics, self-healing devices and touch-sensitive films look to be interesting.

Finally, cybersecurity will go on to be a huge area of growth for semiconductors. Dr. Rhines concluded, "There is huge interest in how chips can be made more secure."

Sunday, April 21, 2013

Optimizing Ethernet networks for mobile access and cloud service delivery

Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).

Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.

Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.

ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.

ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.

Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.

The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.

Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure network for L2 VPN services at 50 percent lower cost than alternative solutions.

Unlock your mobile with SlimPort

Founded in 2002, Analogix Semiconductor Inc., a fabless semiconductor company, has introduced the SlimPort that turns your mobile phone into a game console. It also turns your phone into a PC. SlimPort also turns your phone into a media library and player.

SlimPort is a simple mobile accessory that unlocks the full power of your phone or tablet. Some examples are the LG optimus G Pro, PadFone Infinity, Google nexus and Arrows Tab, respectively.

Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Andre Bouwer, VP Marketing, Analogix, said SlimPort also connects to any TV, monitor and projector. It should not be confused with DisplayPort, an open standard and owned by VESA, MyDP is an extension of DisplayPort. SlimPort is a brand of products that provide access to all of your videos, games, and work, wherever you are. It complies with MyDP.

DisplayPort is everywhere. It drives internal and external notebook screens. TVs need notebook connectivity and 4K x 2K, as do phones and tablets. DisplayPort is architected for mobile. It is used in all PCs today. It offers the highest resolutions and battery charging during display. It supports fixed data frequency and spread spectrum, and has passed EMI tests. It reduces the system power consumption as well as noise, strengthening incoming and outgoing RF signal.

SlimPort connects VGA, DVI, HDMI and DisplayPort. SlimPort performs 1920×1080 at 60Hz, making it ideal for gaming, and 1920×1200 at 60Hz, making it suitable for office. SlimPort charges and preserves the battery. It plays HD audio and video, and you can also plug in USB power to charge your phone.

SlimPort creates value. It is easy to integrate and provides seamless connectivity across the product line. It enables new mobile price points, and allows new bundling opportunities and more data usage. Analogix is not stopping here! It further intends to increase the resolution to 4K, support multi-screen, allow AV+USB data and enterprise security.

Tensilica to expand Cadence IP footprint in SoCs

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon tape-out. It will also strengthen solutions to address key market segments.

Embedded systems trends and developer opportunities

Today, the world is transitioning from independent devices to  connected systems. Intel has been inside the embedded systems market for over 35 years, having developed 270+ CPUs and SoCs as well as 100+ chipsets.

Herb Hinstorff, director of Marketing, Developer Products Division, Intel Software said that Intel has been engaged at all levels of the solution stack. He was speaking at the 13th Global Electronics Summit at Santa Cruz, USA.

There are tools to deliver on developer needs, such as debuggers, analyzers, compilers and libraries. There are tools to provide the deep system-level insights into power, reliability and performance.

On the debuggers side, they increase system and device stability and reliability. There is an efficient system, SoC-wide defect analysis and ultra-fast system-wide tracing for software debug. There is an integrated application level debugger. Overall, it speeds system bring-up and development. Analyzers focus on boosting reliability, power efficiency and performance, enabling differentiated designs, system-wide analysis and deep insights.

Compilers go on to optimize performance and efficiency. There is the industry-leading C/C++ compiler. It boosts system and application performance on Intel Atom, Core and Xeon processors. Compilers also take advantage of the multicore to boost performance.

There are libraries for performance and efficiency. Software building blocks increase the developer productivity and boost performance. There are specialized testing functions that handle signal processing, data processing, complex math operations and multimedia processing. Besides, there is future-proof software investments. The libraries provide an easy way to take advantage of the multicore capabilities to boost performance.

The Intel System Studio is an integrated software tool suite that provides deep, system-wide insights to help accelerate time-to-market, strengthen system reliability, and boost power effiency and performance. The JTAG interface has system and application code running Linux.

There is a continued broadening of the OS support, and a broader range of tools to match the expanding SoC capabilities. There is more extensive software based training and simulation, as well as market-specific libraries and APIs.

Given that the market is transitioning from independent devices to connected systems, more capable SoC platforms and complex software stacks require deeper and broader system-level insights and optimizations. Embedded developers can take advantage of the Intel System Studio to accelerate the time-to-market, strengthen system reliability, and boost power efficiency and performance of the Intel architecture-based embedded and mobile systems.

Algotochip building ecosystem with IP providers in targeted markets

Algorithm-to-chips is Algotochip’s mission. It turns algorithms into chips by converting your behavioral algorithm C-code into architecture C-code into RTL into GDS-II.

Speaking about architecture evolution at the 13th Global Electronics Summit at Santa Cruz, USA, Satish Padmanabhan, CTO and founder, Algotochip, said that the interconnect between CPU and all the HA blocks needs to be determined.

The market approach includes building an ecosystem with leading IP providers in targeted markets. Some areas Algotochip is looking at are LTE and smart grid markets.

Nitto Denko is committed to support Algotochip moving forward. Year 2013 will see significant investment increases in terms of engineering resources, as well as sales and marketing organization to cover USA, China and Japan.

Algotochip is showing that its technology is sound in improving system hardware and software partitioning and first time right design. The LTE turbo decoder performances in terms of throughput, power and gates count is showing the benefits of Algotochip BlueBox. The company is now building an ecosystem around its technology.

ARM Holdings and Tensilica are the first of the few partners that Algotochip wants to collaborate with to improve the overall time-to-market of digital design of the SoC, ASIC and FPGA, etc.

Embedded software: Next revolution in EDA

There is a key lesson that Mentor Graphics made while trying to deliver solutions that were right for software and hardware developers. The lesson was: tailor the software to the discipline! Make it as similar to their environment as possible!!

Delivering his speech at the ongoing 13th Global Electronics Summit in Santa Cruz, USA, Dr. Wally Rhines, chairman and CEO, Mentor Graphics, said that 15 years of acquisitions taught Mentor how to think and behave as an embedded software company.

Open systems requires active engagement in software committees. Each open source project has some form of governance to manage contributions, release plans, etc. There is a community peer selection process for each open source project. About 50 Mentor Embedded Sourcerers are actively involved in the open source and Android communities.

There is a need to take the advantage of knowing both worlds. Mentor’s Sourcery CodeBench is an embedded C/C++ development tool based on open-source standards. Sourcery CodeBench is a complete development environment for embedded C/C++ development on ARM, Coldfire, MIPS, Power, X86, and other architectures. You can install, flash and debug in minutes!

Sourcery CodeBench
Sourcery CodeBench is now the semiconductor industry’s leading embedded toolchain. There is an integrated development environment. It has the GNU compiler (GCC) and optimization tools. It allows debugging and analysis, libraries and QEMU simulator.

There are about ~15,000 downloads per month. There have been ~150,000 downloads and 300 releases per year.

Here's the video! 

CSSPs — custom to catalog solutions from Quicklogic

QuickLogic is a Silicon Valley-based fabless semiconductor company. It is an innovator of CSSPs or customer-specific standard products. It is focused on high-growth mobile markets such as consumer,  enterprise and mobile enterprise.

Speaking at the ongoing 13th Global Electronics Summit in Santa Cruz, USA, Andy Pease president and CEO, QuickLogic, said it does all the drivers that actually need to be inside all the application processors. It is trying to solve the OEM dilemma for mobile market. There are the Android + ARM camp and the Windows + x86 camp, respectively. One way to solve the problem is to do software overlay to Android/Windows.

CSSPs enables the OEM hardware differentiation. It allows fastest time-to-market for custom silicon. It also extends the battery life. The reference designs showcases proven system blocks and capabilities. It is a known good starting point for CSSP development.

The application development dilemma includes optimizing for the specific vertical vs. horizontal markets. When does the integration happen for new standards? Also, how long does a company need to keep mature standards?

QuickLogic has inrtroduced catalog CSSPs. These are ready-to-integrate solutions. They are architectured, developed and verified with application processor vendors.

Platform diversity enables solutions 100 percent programmable for ultimate flexibility. Hybrid programmable/ASIC is provided for common applications requiring some customization. The go-to-market strategy includes complete solutions. It includes software drivers, firmware and application reference codes. It is a collaborative customer model.

A partner challenge could be to re-position its existing AP in new, adjacent markets and applications. QuickLogic’s solution is to provide custom design and software drivers to bridge the AP with camera interface to different types of image capture devices.

Another example is in SD memory. The premier challenge is to adapt the existing baseband processor to emerging market requirements. QuickLogic’s solution is to develop multiple custom designs and software drivers to bridge the baseband with SD memory.

Catalog CSSPs emable the OEM engineers expanded functionality beyond the application processor’s native capability. They expand the served available market of application/embedded processor companies. It scales QuickLogic’s resources across multiple end markets, applications and customers.

Skin inspired electronics for mobile health

Skin inspired electronics can be used for mobile health such as wireless sensor bands, cell phone and computer at doctor’s office, according to Prof. Zhenan Bao, Stanford University. She was delivering the inaugural lecture on day two of the ongoing 13th Global Electronics Summit in Santa Cruz, USA.

There are organic field-effect transistors (OTFTs). The current flow is moderated by binding of molecules and pressure. E-skin sensor functions have touch (pressure) sensors, chemical sensors and biological sensors. There are other flexible pressure sensors such as conductive rubber, which is thick and has hysteresis. Another type is poly-vinylidene fluoride (PVDF) thin film. Yet another type is the OTFT touch (pressure) sensor.

There is an example of the heart pulse measurement. Another related device is the full pulse wave for medical diagnostics such as blood pressure monitoring, detecting arrhythmia, heart defects and vascular diseases. In terms of temperature sensing, Stanford has developed a flexible body temperature sensor made of plastic.

There is chemical sensing as well. These are very stable and can be put in sea water. There are also electronics to mimic the body, such as the biodegradable OTFT. Another example is the transparent, stretchable pressure sensor. Finally, the other attribute of the human skin is self healing. Stanford University also developed the all-self-healing e-skin.

The e-skin concept ‘Super Skin’ has touch pressure sensors, chemical or biological sensors in air – electronic nose and liquid environments – electronic tongue, flexible strechable materials, biocompatible or biodegradable, self-powered — strechable solar cells and self healing.

Xilinx stays a generation ahead!

Today, the challenge is all about abstraction and putting automation around it. Productivity is automation and abstraction. Tom Feist, senior marketing director, Design Methodology Marketing, Xilinx said that the company’s strategy has been about All Programmable abstractions. He was speaking at the ongoing 13th Global Electronics Summit being held in Santa Cruz, USA.

Today’s hardware design abstractions include accelerated time to integration, abstracting hardware. For IP abstractions, Xilinx has introduced the IP integrator. It enables IP re-use and time to integration. The Vivado uses multiple plug-and-play IP. Vivado IP integrator is co-optimized for platforms and for silicon, respectively.

Vivado IP integrator has features such as correct-by-construction and automated IP systems. Vivado high-level synthesis allows C/C++ abstractions. Xilinx introduced the OpenCV library, accelerating smarter vision. It supports frame-level processing library for PS. It also supports pixel processing interfaces and basic functions for analytics.

Mathworks has model based abstraction. The automatic C and HDL code generation is supported from the same algorithmic level.

Hardware/software partitioning is supported for Zynq-7000 AP SoCs.  There are comprehensive video, motor control and signal processing IP libraries. There are automated workflows targeting Xilinx platforms.

Xilinx is also working with National Instruments. The automated C and HDL code generation is from the same graphical syntax in the LabVIEW IDE. It automatically generates a hardware implementation to meet requirements, abstracting Xilinx tool flow. There is a comprehensive software, hardware and I/O platform for creating control and monitoring systems.

Abstraction evolution has evolved to system level abstraction. It is abstracting all hardware through an increasing layer of automation.

All Programmable realization empowers software and systems engineers. There is a common compilation environment for heterogenous systems. It consumes C, C++ or OpenCL and libraries with user directives. There is automated flow — the user determines the program modules that run on various components.

The Vivado Design Suite 2013 abstractions with IP based design, C, C++, SystemC and OpenCV is new. Mathworks and National Instruments system level design abstractions with new levels of automation is emerging. Xilinx’s vision has been to empower the software and systems engineers by extending abstractions and automation.

Exar serving high-growth areas with innovative value-added solutions

Exar Corp., established 1971, is headquartered in Fremont, USA, and has design centers in Silicon Valley and Hangzhou, China. Louis DiNardo, president and CEO, Exar, said that the company’s strategic model is to serve high-growth markets with innovative value-added solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Exar offers solutions that includes high performance analog-mixed signal as well as data management solutions. Its current market focus is on networking and storage, industrial and embedded systems, and communications infrastructure. It is focusing on power management products, connectivity products and data management solutions.

Power management products include those for analog power management such as switching regulators, switching controllers, linear regulators, supervisory controllers, etc, For programmable power, Exar focuses on multiple output synchronous buck controllers.

Some of the products include POWER, the Exar Programmable PowerSuite 5.0. Recently, Calceda has been powering servers with the PowerXR technology.

For data compression and security, Exar is offering hardware acceleration and software solutions meant for compression and decompression, acceleration, encryption and decryption. There are high growth markets supporting social networking, industrial Internet and financial technology as well.

Exar’s Panther I is a first generation compression/security engine with the PCIe interface. The Panther II is a second generation compression and security engine with PCIe and FPGA interface.

Geo creating better user experience with motion detection algorithm

Geo Semiconductor Inc. has been enabling new markets that are changing the world. In automotive, it is into HUDs, Fisheye cameras and digital calibration. In cloud/Skype camera, it is into home monitoring, doorbell cameras, and Skype TV.

According to Brian Gannon, VP Marketing & Business Development, Geo is a four-year old company, built from 20+ years of development  and $300 million+ investment. It has over 50+ customers in production worldwide. All of this IP allows Geo to provide unique, end-to-end solutions to create new markets. He was speaking at the ongoing 13th Global Electronics Summit at Santa Cruz, USA.

Geo has been creating better user experience with motion detection algorithm. Geo’s eWARP processor is a highly efficient hardware block that can be programmed to do any geometric transformation of pixels in real-time.

The eWARP processor is fundamental to camera and projection systems. For the camera, it is correcting distortions, such as wide angle, fisheye, lateral color, etc. It takes care of ePTZ, fisheye, panoramic dewarping and scaling. It is also stitching/blending cameras. Geo provides 3D alignment for stereoscopic cameras as well. Finally, it takes care of the camera optical alignment.

For the projection, the eWARP processor is correcting distortions such as projection optics and keystone correction. It also takes care of ultra short throw, stitching/blending – tiled displays, curved displays and color correction.

Geo provides the only solution that can concatenate multiple transforms. It does multiple independent geometric corrections. An example is enabling real-time ePTZ. There are custom layouts and views, along with real-time HD resolutions up to 60fps. There are up to eight multiple images.

Wide angle lens correction is possible with zero content loss. The heads-up display (HUD) solution corrects for windshield and projector. It simultaneously corrects for any distortion created by the windshield, projector or mirror — instantly and digitally. It removes any alignment parts and electronics in the HUD system. Calibration can be automated to save labor costs.

Geo’s powerful automation software also reduces labor costs and cycle time. For instance, a single eWARP IC can correct, align and dewarp four automotive VGA cameras.

Intelligent evolution of FPGAs

FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.

There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.

Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).

Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.

In addressing power/performance challenges, 20SoC is said to be the  quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC  process is the first 32Gbps transceivers that are operating in 20nm silicon.

Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.

Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.

Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.

Metal MEMS provides future of cell phone radio

Cavendish Kinetics is well known for its combined experience in MEMS, RF system design and CMOS design. Since 2008, it has focused on developing digital variable capacitors to improve wireless connectivity and data rates for mobile phones.

According to Dennis Yost, president & CEO, Cavendish Kinetics, 4G/LTE mobile devices are not yet achieving their potential. Antenna frequency tuning is an essential technology. Only metal MEMS technology has the size and performance. He was speaking at the ongoing Globalpress Electronics Summit 2013 in Santa Cruz, USA.

Cavendish claims to have the team, proven technology and real demonstrated performance. There is IP and patent protection for customers. Cavendish also owns the process.

The future of cell phone radio is needed in order to meet the performance gap. In future, you will see adaptive power amplifiers.

Antenna frequency tuning used in traditional RF applications. How do you ensure there is no loss in the component? Only MEMS has the performance and size for cell phones. Metal MEMS has almost no series resistance. No switches are required.

Previous designs required switches and different loads. Mechanical capacitors change capacitance value by moving plates – changing the area or plate distance changes the capacitance. MEMS capacitors do the same at the micrometer level.

Successful MEMS
Users can control design and manufacturing process of devices. How a MEMS is built is just as important as what you build. Success requires MEMS design expertise, MEMS process expertise and MEMS volume production expertise.

Cavendish has MEMS experts in all areas. It developed and owned MEMS manufacturing process. It uses all standard CMOS foundry technology. Innovations have so far yielded over 100 patents in manufacturing process and MEMS design.

By using the NanoMech technology performance, Cavendish Kinectics has demonstrated excellent performance in a small chip.

Silicon Labs advances digital radio market

As per James Stansberry, VP & GM Broadcast Products, Silicon Labs, there was the emergence of CMOS RF design in late 1990s. He was speaking at the Globalpress Electronics Summit 2013, being held in Santa Cruz, the US.

CMOS strengths can be maximised in low-cost/high-volume wafer processing, low-power and high density logic that scales with lithography, and switched device architectures enable high-performance ADCs and DACs. Large RAM arrays and NVM are also available.

CMOS weaknesses can be minimized if the noise level at given current (1/f noise), there are low Q integrated inductors, Ft still lags SiGe and GaAs at same power level, and there is lower dynamic range with shriking supply voltages.

There are design LNAs, mixers, VCOs, PLLs and ADCs to compensate for CMOS constraints. It is recommended to use digital logic to detect and correct RF and baseband performance deficiencies. Optimizing a CMOS receiver means to design for cost without power or performance compromise and leverage digital signal processing to optimize RF.

Silicon Labs’ multiband radio receiver solution allows the power of integration. It leads to over 80 percent BoM savings. No manual alignment is required. There is minimal rework and superior RF performance. The BoM cost = -$0.10. Silicon Labs will be introducing the Si468x FM digital radio next week.

Advancing digital radio market
The software-defined radio (SDR) is to support multiple digital radio standards. It also supports worldwide analog FM and RDS/RBDS. It is compatible with iBiquity and NRSC-5 standards for FM digital radio and also compatible with Eureka 147 DAB/DAB+.

It is flexible and cost effective, as the radio-on-a-chip solution is available in WLCSP and QFN packages. It supports module or on-board designs. Silicon Labs is looking to broadening digital radio penetration. It can be seen in handheld clock and tabletop radios and clocks, mobile phones, tablets, PMPs and PNDs, and boom boxes and mini/micro systems.

Nanometer an enabling technology

According to Prof. Yi Cui, Dept. of Materials, Science & Engineering, Stanford University, nanometer is an enabling technology. We can do applications such as electronics, energy, environment and health. Some examples are high energy batteries, printed energy storage devices on paper, textile and sponge, etc. He was delivering the inaugural address at the Globalpress Electronics Summit 2013, being held in Santa Cruz, USA.

High energy battery has portable and stationary applications. In portable, energy density, cost and safety are important. In stationary, cost, power, energy efficiency and ultra-long life are important. The standard is 500 cycles at 80 percent. One of the challenges of silicon anodes is that Si has 4200 mAh/g of silicon, 10 times more than carbon.

Nanowires can offer shorter distance for Li diffusion (high power), good strain release and interface control (for better cycle life), and continuous electron transport pathway (high power). In-situ transmission electron microscopy (TEM). Double walled hollow structure provides stable solid electrolyte interphase (SEI). The outer surface is static. Amprius, where Prof. Cui is CTO,  is a $6 million US government funded enterprise. Amprius China started in Nanjing, in April 2012.

Another example is printed energy storage devices on paper, textile and sponge. For low-cost scaffold, paper, textile and sponge, are used. There is cellulose paper and synthetic textile, besides sponge, as well.

There can be transparent batteries. It is actually very hard to develop those. The challenges for making a transparent battery are Al film, cathode, electrolyte, etc. An idea: dimension smaller than eye’s detection limit (50-100 um). Also, grids are well aligned.

Transparent conducting electrodes provide electrical and allow light to pass through. Apps include solar cells, etc. Indium tin oxide (ITO) has a low abundance of indium, brittleness when bent, and sputtering at high cost. Electrospinning of nanofibers is done for transparent electrodes. An example is the trough-shaped nanowires.

Yet another example is the water nanofilters for killing pathogens. The processes available for killing bacteria include chemical disinfection, UV disinfection, boiling, etc.

The first generation product is currently ready at Amprius. Amprius licensed the IP from Stanford. Stanford is also an investor in Amprius.

Friday, April 12, 2013

Brocade intros HyperEdge architecture for campus networks

Brocade has announced its HyperEdge architecture, a unified wired and wireless infrastructure, it claims is as dynamic as its users.

Edgar Dias, regional director and country manager, India, said that mobility Is redefining how we access information and connect to each other. By 2020, there are likely to be over 30 billion connected things, with over 200 billion with intermittent connections.

The number of wireless devices connecting to the corporate network has been exploding. It is estimated that by 2016, two-thirds of the mobile workforce will own a smartphone, and 40 percent of the workforce will be mobile.

Healthcare is revolutionized by mobility. About 80 percent of remote patient monitoring will be by mobile devices by 2016. Education engages with wireless devices as well, with universities projected to spend more than $837 million on WiFi access points and controllers in 2013. About 22 percent of pupil-facing computers will be tablets by 2015.

The three things required from a campus network solution include reduced complexity, integrated wired and wireless, and investment protection. Mobility changes the game for all organizations and their IT departments. The campus network takes center stage in staying competitive.
Brocade's HyperEdge architecture is agile, as there are collapsed network layers with active links and intelligent wireless AP traffic management for mobile users. It is also automated, simplified with reduced management touch points, and self discovery and configuration of wired and wireless devices. Lower cost of acquisition and operation makes it cost effective.

HyperEdge innovation radically simplifies management, and improves performance. Distributed services such as advanced features and capabilities are propagated across premium and entry level switches. Consolidated management leads to shared switch configuration and network policies, automated management and software updates.

There are active-active links that eliminates STP to improve efficiency and performance. Multichannel trunking is available to scale and interconnect. Distributed AP forwarding leads to intelligent access points route traffic locally to avoid controller bottlenecks. There is the centralized AP management, where controller based management keeps costs low and coverage levels high. Lastly, there are self-healing access points that automatically adjust to maintain coverage in the event of an access point failure.

Wednesday, April 10, 2013

New set of rules in IGBT market

The insulated-gate bipolar transistor (IGBT) is a three-terminal power semiconductor device. The main trends impacting IGBT include the power stack trend, revolution of Chinese IGBT, growth of IGBT use in consumer applications, and competition from SiC and GaN based devices.

According to Alexander Avron, Yole Developpement, current density of the IGBT has been multiplied by 3.5 in 20 years. IGBT technology is now very mature, using trenches and thin wafer. Wafer size for IGBT production is still growing and Infineon is currently the leader.

Infineon expects a cost advantage of 20-30 percent by increasing the wafer size from 8- to 12-inches. For Infineon, the 12-inch production line is for MOSFETSs, and they will probably produce IGBT 600V on thin wafer. Fairchild and IR prefer to remain at 8-inch.

Technology roadmap
A new generation release is always a low voltage product (600-900V). Main improvements have been in losses reduction. In the IGBT supply chain, vertically integrated companies are Japanese only, besides a few, like ABB. Only a few companies, like Danfoss, take advantage of  doing module and inverter for motor drives. In a cost-driven market, there is not much competitive advantage in developing own module.
Trends impacting IGBT
The power stack trend - The need for more modularity and higher performance made components makers (active and passive) to join and create consortiums or JVs. It is trending toward more integration.

Revolution of the Chinese IGBT - First Chinese companies are starting to manufacture IGBTs using standard technology and low cost, perfect for a local market. Asian players are becoming a greater part of the IGBT market. While they do not make a lot of devices as yet, it is expected that they will quickly gain market shares in low cost local businesses.

Some new entrants include CSMC, Hua-Hong NEC, PSMC, BYD, Grace Semiconductor, Alpha & Omega Semiconductor, etc. Many Chinese companies are very close to or already able to manufacture their own IGBTs. This will grow and create a Chinese IGBT.

Growth of IGBT use in consumer applications - IGBTs are becoming more part of the consumer lifestyle. Renewable energies and EV/HEV are good examples. Pioneers of HV IGBT have the best market shares. Margin for HV IGBT modules is high. It is first in the EV/HEV and renewables markets. New markets are targeted by all players.

The ASP evolution of consumer markets has dropped down very fast as compared to the industrial markets. Also, DLB or direct lead bonding is a specific technology from Mitsubishi Electric to produce epoxy molded power modules for hybrid and electric cars. Mass production is targeted for 2013.

Competition from SiC and GaN - Next generation devices are becoming available. They will displace IGBT, but not at all the levels and in all the applications. Characteristics of GaN-based inverters are: they primarily target medium voltage apps (200-600V range). SiC diodes are already in production, mainly coupled with IGBT. Penetration of SiCs in wind turbines will happen later than expected.

As for the 2006-2020 power devices market forecast, Yole expects a more stable growth by 2020. There was an unanticipated slowdown in 2012. The market share in 2011 was Mitsubishi 27 percent, Infineon 23 percent, Fuji Electric 11 percent, etc. The IGBT market share was Infineon 35 percent, Mitsubishi 32 percent, Hitachi 12 percent, ABB 9 percent, respectively.

Yole estimates that at least 15 companies - foundries, fab lights and fabs -- are working on IGBT development in China.

Tuesday, April 9, 2013

Five-year outlook for solar PV industry!

According to Finlay Coville, VP and team leader, NPD Solarbuzz, full year end market PV demand during 2012 reached 29.05 GW. The demand is forecast to increase to 31 GW in 2013. China is expected to replace Germany as the leading market for the first time. The global market is likely to have a CAGR exceeding 15 percent, highlighting long term confidence in global PV adoption levels.

Supply vs. demand overview in 2012
The upstream c-Si module/thin-film panel suppliers produced 30.1 GW of new product in 2012. Combined with inventory levels through the value chain, this provided 31 GW of panels to the downstream channels. 29 GW was used for market demand, while 2 GW went to the downstream inventory.

Demand overview 2013
Year 2013 is shaping up as a 31 GW demand year under the most likely scenario. Over 50 percent of the end market demand is projected to come from China, Germany and North America (USA and Canada). 2013 will be a transition year for the emerging PV territories. Both the Middle East and Africa and Emerging Asia will likely reach 1 GW.
PV demand in 2012 accounted for approximately 30 percent of all PV installed globally. The industry growth in 2012 is positive, but set against a backdrop of an industry that had been accustomed to year-on-year growth often exceeding 100 percent. The industry is forecast to return to double digit growth.

PV scenario forecasting continies to show divergent outcomes in 2017. A high market demand scenario assumes a strong economic environment and aggressive PV policies by way of direct incentives and lower regulatory hurdles.

Five-year cumulative demand by geography
Cumulatively, global PV demand is forecast to exceed 230 GW over the five year period to 2017. China is forecast to install 51 GW accounting for over 20 percent. Europe will continue to offer strong regional PV market. North America and Japan will provide over 61 GW of demand. Emerging markets are projected to create over 25 GW of PV demand, more than 10 percent of the cumulative total to 2017.

By application segment, the ground-mount segment will remain the single largest segment over the five years. Residential and non-residential (commercial) segments will continue to be characterized by specific end-user requirements, different supply channels and routes-to-market for upstream suppliers.

The PV industry was configured to supply over 45 GW in 2012. The industry is likely to be in an over-capacity mode in 2013, with balanced supply/demand levels restored from 2015. Market share aspirations remain a key driver for PV manufacturers. During 2013 and 2014, the capacity taken offline is likely to be more than compensated for by newly ramped capacity.

With multi-domain c-Si module production, most panels had efficiencies in the 13-16 percent band during 2012. High efficiency concepts are not likely to strongly influence the module efficiency landscape during 2013 or 2014. If high efficiency cell types gain traction, the share of modules with efficiencies above 16 percent will increase.

In 2012, a wide range of efficiencies were produced, but with levels that do not compete with c-Si modules for space-constrained applications. The range of panels available in the 12-14 percent band is likely to grow strongly from 2015 as leading suppliers benefit from process improvements. Panels below 10 percent efficiency will become obsolete.

Despite end market growth expected, revenues available to each part of the value-chain will see strong declines Y/Y in 2013. This is due to the ASPs declining at a faster rate than the end-market demand growth, within a strong overcapacity environment. Revenues are also unlikely to recover for each value-chain segment until the 2016-2017 period.

What's with prices?
2012 was the fourth year in a row that c-Si module prices declined and was the largest Y/Y decline. As capacity throughout the PV chain has increased, the oversupply has put further pressure on the ASPs. Declines in pricing occurred further upstream, at the poly, wafer and cell segments.

Tracking SAM revenues fron selling modules into downstream channels is becoming less important to the PV industry. as a number of module suppliers take on EPC and project developer roles.

PV equipment spending
As for PV equipment spending, the most likely forecast sees capacity being added by a select gtoup of tier 1 c-Si makers during 2014. The next cyclic downturn is forecast for 2016-2017. This assumes excess capacity is added in the next upturn.

If we look at the current scope of trade disputes, there are five major markets -- EU, USA, India, Canada, China -- investigating products being imported, with China featuring in most cases. Most disputes are being pursued by the internal bodies, but several have been referred to the WTO for review. A growing number of emerging PV regions already have domestic content incentives.

PV demand was 29 GW in 2012, and 2013 is forecast to tip 31 GW. 230 GW of new PV demand is forecast between 2013-2017, adding to the 100 GW at the end of 2012. Eighty percent of PV demand in 2013-2017 will come from the top 10 end markets.

Tuesday, April 2, 2013

Critical success factors for MEMS commercialization

MEMS still has a long way to go to meet the challenges of commercialization! Critical success factors include efficient process transfer from breadboard to production. There is a need to pay attention to customers' needs. More resources need to be adopted from the semiconductor industry, said Roger Grace, president, Roger Grace Associates.

There is a need to create significant awareness as to the unique solution benefits of MEMS based system solutions. Firms need to better understand customer/market needs. There is a need to establish defensible product differentiation.

Emerging opportunities include single MEMS based system solutions, especially in analytical instruments, double magnetic MEMS, triple point-of-care bio, energy harvesting/storage, etc. There are barriers to commercialization of MEMS. Until recently, it is plagued by lack of high-volume apps. There is lack of well-defined direction from roadmaps, industry standards and associations. Packaging and testing costs are typically at 70 percent of total value. There is also a lack of focus on customer needs and lack of capital formation opportunities, risk averse investors.
Besides, successive bubble busts, i.e., biomems, optical telecom, have seen wary investors. There are very fragmented markets, many small companies and few large players. Also, there are limited 'success stories' of MEMS/MST companies, eg., Invensense. There are new market opportunities for large volume apps, eg. in automotive, CE, etc.

Downturn hit research hard! R&D remains a novelty for most firms. Now, there is an increase in university and R&D labs for MEMS development. There is still plenty of R&D available from DARPA, SBIR and STTRs. Now, we are seeing a healthy amount of activity in new devices and systems research.

As for DfM (design for manufacturing), Invensense's 'shuttle' process may finally become a usable standard. New approaches are also changing the paradigm of cost structure. Examples are Invensense gyros, Freescale chip-stacking accelerometers, ST, etc.

While there seems to be strong MEMS infrastructure, there is some fraying at the ends. The industry needs to remain competitive and lean. As for profitability, while the margins don't seem great for high volume MEMS devices, they are holding on somewhat. The general consensus of the VC community has been that MEMS has lot of growth potential, but it doesn't have a good track record of producing profitable firms, as yet.

The lack of DfM emphasis and the absence of a coherent package and test capability is the lack of management insight. As for standards, the creation of the first Standardized Sensor Performance Parameter Definitions is a huge step in the right direction.