Tuesday, October 30, 2012

III-V high mobility semiconductors for advanced CMOS apps

Clement Merckling, imec, Belgium, presented on the epitaxial growth and in-situ passivation requirements for III-V high mobility semiconductors for advanced CMOS applications at the Semicon Europa in Dresden, Germany.

The motivations for III-V MOS transistors include higher electron carrier mobility (@ low-field), more efficient source injection, smaller energy bandgap, VDD scaling, band engineering capabilities, lower temperature processing, high-K gate first process possible and 3D compatible architecture.

The International Technology Roadmap for Semiconductors (ITRS) believes in Ge and III-V. IMEC epi + in-situ oxide 'tool park' involves MBE (molecular beam epitaxy) and MOVPE (metalorganic vapour phase epitaxy) III-V growth techniques. The III-V EPI is clustered with in-situ oxide capabilities.

The AIXTRON Crius 300mm looks at III-V selective epitaxial growth (III-As and III-P). The AMAT/RIBER III-V logic cluster 300mm looks at the III-V selective epitaxial growth (III-As and III-P), in-situ surface analysis, handled by RIBER ISA 300, and oxide (ALD and MBE) chambers in-situ.

The RIBER MBE 49 cluster 200mm looks at the III-V solid source epitaxy (III-As and III-Sb) oxide chamber in-situ.

Main issues and challenges
Main issues for III-V integration include III-V integration on Si platform. There are all sorts of crystalline defects. Next, gate stack formation on MOS. It is much more difficult to passivate interfaces. Smaller bandgap, means, an increased Ioff due to band-to-band-tunneling.

Challenges with III-V heteroepitaxy on Si include Lattice mismatch, anti-phase boundaries (APB), mismatch stress relaxation and related defects such as dislocations at interface, and extended defects (threading arms, SFs). There are other defects caused at isolation interfaces, such as twins, stacking faults, facets, etc. Finally, there is interdiffusion at heterogeneous interfaces.

However, it is possible to achieve high quality heteroepitaxy by direct epitaxy using metamorphic buffer and defect confinement and wafers bonding. Strain relaxed buffer (SRB) is among the options for III-V materials integration at imec.

There can be InGaAs metamorphic buffer, with the MBE growth of low defect density and device quality III-V heterostructure using a suitable metamorphic buffer. Or, there can be III-Sb on Si by SS-MBE, that provides a route to relax III-V.

Defect confinement is possible via 'necking effect'. The selective area growth (SAG) of III-V compounds via MOVPE (or CBE ?) means the defects are trapped at trench edges. The other way is dislocation trapping in narrow STI trenches for aspect ratio >2. There is low defect density material in the upper part of the trench.

Elimination of APBs for on-axis Si (001), Si recess engineering, is possible either via rounded-Ge surface or V-grooved surface. In the rounded-Ge surface, step creation is done by surface engineering of a Ge seed layer. Double steps on a Ge surface are more stable and easy to form with a lower thermal budget than on Si.

In V-grooved surface, (111) surface is obtained either by KOH or TMAH wet etching. Growth inside a pre-defined Si {111} enclosure promote initial III-V nucleation uniformity.

The 'necking effect' approach presents its own challenges. One, perpendicular view, where there is efficient defect necking effect with side wall and parallel view, which allows viewing high defect density.

Friday, October 26, 2012

Yet another electronics policy for India?

India has once again announced an Electronics Policy, and frankly, I’ve lost count, how many times! Nevertheless, one hopes that this policy somehow takes off, and helps India get off the ground!  There are certain points in the policy that are worth a relook.

One, the setting up of electronic manufacturing clusters. This has been time and again stressed and re-stressed. Will it come around, this time? Let’s wait and watch, if it happens this time!

Two, as per the policy, there is a proposal for setting up two semiconductor wafer manufacturing fabrication facilities. Where? As far as one knows, there is hardly any infrastructure around to support even one semicon fab! Some people may say, Bangalore, but well, they are welcome to say that! As for people buying more of ‘domestically manufactured electronic goods’, it remains to be seen!

Three, back in 2007, when the SIPS program was announced, there were great expectations! If you recall some time ago, I mentioned that the Indian semiconductor policy, announced back in 2007, had supposedly expired on March 31, 2010! Then, the Indian industry came up with recommendations that included extending the Indian semicon policy up to March 2015! So, what happens to that? Or, is it dead and buried?

Four, back in 2007, the ‘ecosystem units’ were clearly defined as units, other than a fab unit, for manufacture of semiconductors, displays including LCDs, OLEDs, PDPs, any other emerging displays; storage devices; solar cells; photovoltaics; other advanced micro and nanotechnology products; and assembly and test of all the above products. What’s happening now?

Five, does all of this mean that the role of India-based semiconductor companies as a percentage of the semiconductor market globally, will improve? Or, do we take India as a system/gadget maker and thus, as a percentage of that market??

Six, fabrication is increasingly expensive, much involved and the actual global fabrication players are declining and will be about three to four companies. There is talk of 450mm fabs across the world! Have we even heard a word from India?

Okay, so let’s say, India will have two fabs? By when? What process technology? If it is a 450mm fab, India can very well kiss goodbye to this decade, at least. And, India continues to slip back in having a ((proper) fab!

Monday, October 22, 2012

IEF 2012: Turning recession into opportunity!

Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:

Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.

Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.

With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.

John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.

This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.

These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.

Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.

Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.

As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.

Wednesday, October 10, 2012

Global semicon sales to drop 1.7 percent in 2012?

This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.

According to the WSTS’s August (posted Oct. 9th, 2012 on its website) actual global semiconductor sales of $23.013 billion, the updated monthly forecast expectation for full year 2012′s total global semiconductor sales is expected to be $294.6 billion as calculated by the Cowan LRA forecasting model.

This latest update to the 2012 sales forecast estimate corresponds to a year-over-year sales growth expectation of minus 1.7 percent, which dropped from the previous month’s year-over-year sales growth forecast estimate of minus 0.5 percent.

It is also lower than the joint WSTS/SIA Spring 2012 sales growth forecast (published in June of this year) of plus 0.45 percent which corresponds to a global sales forecast estimate of $300.9 billion. Therefore, the model’s latest monthly sales forecast output (based on the just announced August 2012’s actual sales) continues to project even more negative sales growth for 2012 compared to 2011 and has remained negative for the third month in a row.

The model’s previous month’s forecast expectation for August’s actual sales was $24.8 billion as shown in the first table. This forecasted sales number generated last month was much higher than the just published actual August sales of $23.013 billion (larger by $1.76 billion or down 7.1 percent). This results in an M.I. (Momentum Indicator) of minus 7.1 implying that the sales growth trend will be ‘marginally’ down (that is, more negative) over the near term forecast horizon.

Incorporating August’s just published actual sales number into the Cowan LRA forecasting model also produces the latest updated sales and sales growth forecast expectations for the remaining two quarters of 2012 as well as for the four quarters of 2013.

These results are summarized in the first table. Also provided in the table are the corresponding previous month’s sales and sales growth forecast numbers which were determined last month thereby providing sequential monthly forecast estimate comparisons.

As displayed in the table, the latest projected full year 2012 global semi sales forecast estimate decreased to $294.6 billion from last month’s sales forecast expectation of $298.0 billion, a decrease of $3.5 billion or down sequentially by 1.2 percent. Correspondingly, the updated 2012 sales growth forecast expectation declined to minus 1.7 percent from last month’s sales growth forecast estimate of minus 0.5 percent, a decrease of 1.2 percentage points, still remaining in the negative territory; however, more negative than last month.

Tuesday, October 9, 2012

Virtual prototyping ready for masses

Device volume, variety and complexity are only going to increase. Transformative technologies like virtual prototypes give organizations the tools to transcend challenges. Companies like Altera are creating competitive advantage and innovation with these solutions. Virtual prototyping is now ready for the masses.

Industry trends and challenges make virtual prototyping a must-have solution. New realities make prior adoption barriers mere myths. Virtual prototyping has become a key process for early software development and supply chain enablement. Industry trends also alter design requirements. For instance, earlier, it used to be computing and single core, which has since moved on to connectivity and multi-core.
This opens up implications for SoC development, especially, in terms of increased complexity and volume of software. There is a need to get the architecture right. No amount of downstream tools will compensate for the fundamentally wrong architecture. There is also a need to start software development earlier, in parallel with hardware design. Needless to say, hardware-software integration must be accelerated and system validation will minimize waterfall development process.

New realities of prototyping render prior barriers as mere myths. For instance, earlier, it was believed that creating a prototype is hard. IP models, TLMCentral and model creation software have come a long way, in reality. Earlier, there was a need to wait for complete prototype. Now, software can be developed incrementally and VDKs are jumpstarting the software development. Earlier, one felt the need to change software environment. In reality, the very same tools, debuggers and environment used for hardware can be used here.

Also, today, there are multiple use cases, verticals and customers of virtual prototyping. There is industry support for system-level models. The TLMCentral is an open, web-based portal that provides consolidated access to transaction-level models available across the industry, helping virtual prototype developers accelerate the creation and deployment of their prototypes for early software design.

Open and free, TLMCentral is the first industry-wide portal to aggregate available transaction-level models. It has over 1,000 models of most common IP blocks and interfaces for wireless, consumer and automotive applications. TLMCentral is supported by leading IP vendors, tool providers, service companies and universities. It also offers model developers, architects and software engineers an infrastructure for news, forums and blogs.

Integrated into the software development environment, there are popular debuggers, powerful controls and debugging information. VDK is a great starting point and for ongoing use. One can install and start using. There is no need to wait for months for a prototype. Templates, sample software and reference prototypes are available in one place. Post-silicon support and validation is provided, besides early availability for software development and testing.

Key process for earlier software development includes hardware-software integration and system validation. Semis are engaging customers earlier. The VDKs are driving tangible time-to-volume reduction. Tangible benefits of virtual prototyping include faster time to revenue, faster customer success, and faster field and ecosystem readiness.

Monday, October 8, 2012

MEMS to be $21 billion market by 2017: Yole

The MEMS market is on a growing curve again, and many changes are happening on the technical side, business model side and supply chain side. MEMS will continue to see steady, sustainable double digit growth for the next six years: 13 per cent CAGR in revenues and 20 per cent CAGR in units. MEMS will grow to $21 billion market by 2017.

Every year brings new business to the MEMS landscape. Combo sensors are coming. The MEMS market is still very fragmented, with a number of high volume MEMS applications still limited today. However, a whole range of new MEMS devices has now reached the market and new ‘emerging MEMS’ devices are coming..

MEMS applicable to mobile devices (RF MEMS switches, oscillators, auto-focus) have the possibility to ramp up to large volumes quickly. Growth will also come from existing sensors that are expanding into new market spaces: e.g. pressure sensors for consumer.

Consumer/mobile applications are driving about 50 per cent of the total volume. Telecom and medical applications will grow faster with expected CAGR of ~20 per cent in the next five years. Industrial MEMS applications represent significant opportunities with grow of ~13 per cent likely.

MEMS in 2011
Four devices represented over 50 per cent of units shipped in 2011. Microphones, accelerometers, gyroscopes and magnetometers represented more than 50 per cent of MEMS units shipped in 2011.

Accelerometer, gyroscope and electronic compass growth is coming from the detection of movement, which is reaching every applications, from mobile phones to pacemakers to smart munitions. Microphone has found a sweet spot in the mobile phone business, replacing the electric condenser type of microphones.

All these devices are about to be combined with other sensors and electronic functions/processing in order to add more value. Multi-microphone arrays with noise cancellation functionalities are now a new feature in smartphones. Accelerometers plus gyroscopes plus electronic compasses are being combined (in a SiP package, in the near future, in silicon SoC) to bring a higher level of functionality at even lower costs.

Invensense achieved the same MEMS size when moving from 2-axis to 3-axis gyros (ITG-3200). As for MEMS accelerometer roadmap, new packaging concepts (such as metal-to-metal wafer bonding, WLP/TSV technologies) are driving the ‘Moore law’ of the MEMS technology roadmap.

In an example of STM accelerometer using TSV technology, by removing the area reserved for I/O pads, the TSV process allows the MEMS die area to be shrinked by 25 per cent compared to the standard accelerometer. However, TSV adds major manufacturing changes that increase the final wafer cost by about $90. The wafer extra cost cumulated with a shrinked MEMS die, makes the final die cost still competitive.

In the 2011 MEMS ranking of the top 30 players, TI, STMicro, HP and Bosch are the ‘big 4′ players with annual revenues of > $700 million. The top 30 accounts for ~80 per cent of total MEMS market. More than 25 players generate annual revenues from $50 million to $300 million.

As for 2011 MEMS foundry rankings, some MEMS IDMs have been successful in developing a MEMS foundry business beyond internal needs. STMicro is by far the no. 1 with key customers such as HP (related to ink-jet MEMS manufacturing). Sony has Knowles’ silicon microphone wafer manufacturing business.

Pure play MEMS foundries include Silex (SW), DALSA (CA), apm (TW), IMT (US), tMt (TW) and DNP (JP). CMOS wafer foundries are entering the MEMS manufacturing space with TSMC (TW), umc (TW), Globalfoundries (SG), SMIC (CH), X-Fab (GE) and Semefab (UK).

The 2011 MEMS foundry services accounted for ~6 per cent of the total MEMS market ($623 million). In 2010, the ratio was similar. Now, there are more and more fabless companies in the MEMS space! There are over 70 fabless MEMS companies.

Wednesday, October 3, 2012

TSMC on 450mm transition: Lithography key!

TSMC unveiled its schedule for 450mm mass production at the recently held SEMICON Taiwan 2012 450mm Supply Chain Forum. Focusing on lithography as the key, Dr. C.S. Yoo, senior director of the 450mm program at TSMC, noted that IC makers and equipment suppliers should fully leverage the G450C. They need to work and innovate to make the 450mm transition a great success.

TSMC has always been in the relentless pursuit of technology innovation. It has been part of all of the computing waves that have driven the market growth. Right now, mobile computing is the leading market driver. TSMC has been helping the industry produce comprehensive, powerful mobile computing devices.

The future growth drivers and trends include mobile computing, cloud computing and smart devices. However, technical and economic challenges also lie ahead. TSMC has been pushing the lithography roadmap. 28nm is said to be the limit of conventional single-patterning lithography. TSMC has innovations to extend immersion to 20nm. The next-generation lithography (NGL) is being preferred beyond 20nm. Also, EUV and multiple-e-beam concept and feasibility has been proven. The more than 10x throughput gap requires collaborative innovation and funding.

TSMC continues to invest in R&D for transistor architecture trends. There is increasing technology complexity, as reflected by mask layers increase. The technology shrink also leads to design complexity.

There are challenges such as intrinsic wafer cost parity and uncertain technology migration ROI. TSMC’s mission is to be the trusted technology and capacity provider for the global logic IC industry for years to come. TSMC already has capacity leadership. TSMC’s total 12″ cleanroom space will equal more than 32 World Cup football fields by the end of this year..

TSMC customers’ expectations include the offer of leading-edge technology, continue to expand capacity, enable faster time to market, faster technology ramp up, faster manufacturing cycle times, and lower cost /die. To bridge the cost and productivity gap, TSMC no longer maintains cost/transistor trend by 2018 due to the slowing pace of technology shrink, and increasing technology complexity.