Xilinx intros 7 Series FPGAs

Xilinx has introduced its 7 Series FPGAs that claim to slash power consumption by 50 percent. These also reach 2 million logic cells on the industry’s first scalable architecture.The company has introduced the Virtex-7, Kintex-7, and Artix-7 FPGA families, which promise:
– 2X more usable performance.
– 2X better price-performance with new class of FPGA.
– 2X better system-performance with Ultra High End FPGA.
– Innovative Virtex-based high volume offering.

Power is said to be the key limiting factor. At Xilinx, it is the top priority at 28nm. The Xilinx 7 Series pushes the boundaries for FPGAs. The three new families are based on a unified architecture.

The Artix 7, when compared to Spartan-6, gives 30 percent more performance, 35 percent lower cost, 50 percent less power and 50 percent smaller footprint. The Kintex 7, when compared to Virtex-6, gives comparable performance, 50 percent lower cost and 50 percent less power. Likewise, the Virtex 7, when compared to Virtex-6 is 2.5x larger, and provides up to 2M logic cells, 1.9Tbps serial bandwidth, up to 28Gbps line rate, and EasyPathcost reduction.

Users can easily scale applications with Series 7 unified architecture and design portability. Enhanced productivity is possible with Targeted Design Platforms. The foundation for Xilinx’s next generation Targeted Design Platforms are:
* Optimized ISE Design Suite.
* Expanded eco-system enabled by Plug and Play AXI based IP.
* Targeted reference designs accelerate development.
* Scalable boards using FMC Base.

Victor Peng, senior vice president, Programmable Platforms Development, Xilinx, also touched upon Programmable Foundation for Extensible Processing Platforms (EPP). It has unrivaled levels of system performance and integration, and ARM based software centric design environment.

This 7 Series will drive the next wave of FPGA adoption, thanks to:
* Increasing market demand for bandwidth coupled with flexibility.
* 2x improvement in power/performance/ capacity/price.
* Major productivity boost with Targeted Design Platforms.
* Fewer ASSPs to choose from/ASICs too risky.