Wednesday, October 12, 2011

Altera launches SoC FPGAs

Altera Corp. has introduced SoC FPGAs that integrates an ARM processor with the FPGA. The SoC FPGAs are said to deliver reduced board space, power and system costs, as well as increased performance. Altera also launched the FPGA industry’s first Virtual Target that enables immediate device-specific application software development prior to hardware availability.

The ARM-based FPGAs integrate 28-nm Cyclone V and Arria V FPGA fabric, a dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect into a single chip. The Cyclone V and Arria V SoC FPGAs further extend the portfolio's reach into the embedded processing market. Embedded developers needs include increased system performance, reducing system power, and reducing board size as well as system cost. ARM + Altera = SoC FPGAs.

The SoC FPGA family highlights include the dual-core ARM Cortex-A9 MPCore processor, which includes hard memory controller, peripherals and high-bandwidth interconnect. Altera’s 28-nm FPGA fabric involves the Cyclone V SoC FPGA the and Arria V SoC FPGA, respectively. ARM’s ecosystem and Altera’s hardware development flow is also featured in the form of the Quartus II software and Qsys system integration tool. These also have a proven virtual prototyping methodology in form of SoC FPGA Virtual Target for device-specific software development.

The ARM processor has been combined with hard IP. The SoC FPGA uses the dual-core ARM Cortex-A9 MPCore processor that features 800 MHz per core (industrial grade), NEON media processing engine, single/double precision floating point unit (FPU), 32-KB/32-KB L1 caches per core and ECC-protected 512-KB shared L2 cache. The hard IP features multi-port memory controller with ECC, such as DDR2/3, mobile DDR, LPDDR2, as well as QSPI, NAND flash, NOR flash memory controller with ECC, and a wide range of common peripherals.

The advanced 28nm low-power (28LP) FPGA fabric is the optimal choice for addressing today’s power- and cost-constrained applications and boasts the lowest absolute power. The hard IP features up to three memory controllers with ECC, variable precision DSP technology, up to two hard PCIe Gen 2 x4 and high-speed transceivers operating up to 10 Gbps.

System-level benefits of SoC FPGA
System-level benefits of the SoC FPGA include increased system performance such as 4,000 DMIPS for under 1.8W, up to 1,600 GMACS, 300 GFLOPS DSP, >125 Gbps processor to FPGA interconnect and cache coherent hardware accelerators. It offers reduced power consumption -- up to 30 percent power savings vs. a 2-chip solution.

There is reduced board size with up to 55 percent form factor reduction and as few as two power rails. All of these lead to reduced system costs leading to lower component cost and reduction in PCB complexity and cost -- less routing with fewer layers. The SoC FPGA device portfolio is tailored to address diverse application requirements.

As for the SoC FPGA design flow, it features a standard hardware development flow using Quartus II software and Qsys system integration tool. The ARM software ecosystem is present with tools, OSs and middleware. The virtual prototyping environment enables immediate device-specific application software development prior to hardware availability. It moves the code quickly to final hardware and shortens time to market.

Boasting the FPGA industry’s first Virtual Target, there is immediate device-specific software development that are binary- and register-compatible. It uses proven virtual prototyping technology, and is Linux and VxWorks enabled, compatible with ARM tools. The SoC FPGA also has the FPGA-in-the-loop extension option.

It facilitates advanced embedded system integration by enabling rapid development of high-performance systems. Features include network-on-chip interconnect technology that supports ARM AMBA AXI interface, Avalon memory mapped and Avalon streaming interfaces. The SoC FPGA also leverages productivity-enhancing hierarchical design flow and simplifies IP re-use.

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