Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET.
the uniqueness about the Cadence Quantus QRC Extraction solution? KT
Moore, senior group director – Product Marketing, Digital and Signoff
Group, Cadence Design Systems, said: "There are several parasitic
challenges that are associated with advanced node designs — especially
FinFET – and it’s not just about tighter geometries and new design
rules. We can bucket these challenges into two main categories:
increasing complexity and modeling challenges.
customers consistently tell us that, for advanced nodes, and especially
for FinFET designs, while their extraction runtimes and time-to-signoff
is increasing, their actual time-to-market is shrinking and putting an
enormous amount of pressure on designers to deliver on-time tapeout. In
order to address these market pressures, we have employed the massively
parallel technology that was first introduced in our Tempus Timing
Signoff Solution and Voltus IC Power Integrity Solution to our
next-generation extraction tool, Quantus QRC Extraction Solution.
QRC Extraction Solution enables us to deliver up to 5X better
performance than competing solutions and allows scalability of up to
100s of CPUs and machines."
Support for FinFET features
How is Quantus providing significant enhancements to support FinFET features?
extraction is at the forefront with the introduction of any new
technology node. For FinFET designs, it’s a bit more challenging due to
the introduction of non-planar FinFET devices. There are more layers to
be handled, more RC effects that need to be modeled and an introduction
of local interconnects. There are also secondary and third order
manufacturing effects that need to modeled, and all these new features
have to be modeled with precise accuracy.
and turnaround times are absolutely important, but if you can’t provide
accuracy for these devices — especially in correlation to the foundry
golden data — designers would have to over-margin their designs and
leave performance on the table.
How can Cadence claim
that it has the 'tightest correlation to foundry golden data at TSMC vs.
competing solutions'? And, why 16nm only?
to Moore, the foundry partner, TSMC, asserts that Quantus QRC
Extraction Solution provides best-in-class accuracy, which was
referenced in the recent press announcement:
Quantus QRC Extraction Solution successfully passed TSMC’s rigorous
parasitic extraction certification requirements to achieve best-in-class
accuracy against the foundry golden data for FinFET technology.”
structures present unique challenges since they are non-planar devices
as opposed to its CMOS predecessor, which is a planar device. We
partnered with TSMC from the very beginning to address the modeling
challenges, and we’ve seen many complex shapes and structures over the
year that we’ve modeled accurately.
surprised that TSMC has recognized our best-in-class accuracy because
we’re the leader in providing extraction solutions for RF designs.
Cadence Quantus QRC Extraction Solution has been certified for TSMC 16nm
FinFET, however, it’s important to note that we’ve been certified for
all other technology nodes and our QRC techfiles are available to our
customers from TSMC today."