Monday, October 22, 2012

IEF 2012: Turning recession into opportunity!

Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:

Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.

Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.

With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.

John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.

This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.

These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.

Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.

Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.

As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.

Joe Sawicki, VP & GM Design To Silicon Division, Mentor Graphics, presented on ‘Retooling Design-For-Test Flows To Maximize Quality & Optimize Cost’: Design-for-test and the final manufacturing test program can be determining factors in the success of new advanced-node products. Even if a new device has all the needed functionality, gadgets and features, and is delivered on schedule and at cost, inadequate manufacturing test at wafer or package can sink an otherwise successful product.

Especially in the world of safety-critical applications like automotive, medical, and aerospace, where zero defects-per-million (DPM) is the requirement and not just the goal. For these applications test quality can have life or death consequences. Conversely, if your test program adequately screens for manufacturing defects, but it cost you more to test the product than you can sell it for, then you will have a quality product that is not commercially viable.

Ensuring that you’re shipping defect-free parts and that test costs are optimized to provide maximum profit margins are critical factors that need to be part of the product design process. Now is the ideal time in investigate the latest test technologies and methodologies to see how they can help optimize quality and cost tradeoffs and help ensure the success of your next product.

Nigel Toon, president Europe, XMOS Ltd, presented on the State Of Semiconductor Start-Ups: The recent trend for semiconductor start-ups has been to build a technology that targets a clear vertical market opportunity. This type of business has the benefit of creating a very clear customer focus. In many cases these vertical focused companies need to drive standards and build eco systems to support the new system level solution. The challenge with this type of business is rather than just building a chip it is necessary to build a complete system solution.

The value of the technology to customers is in the cost, power, physical size, and performance of the total system solution – many times the chip simply becomes a delivery mechanism for the system and a way to charge for the technology. With this type of company it is often a race to build a complete solution and build a market for the system before larger companies see the opportunity.

This means that not only is a silicon team required but a large system software team is necessary as well as a team capable of building a production ready reference design.

This all involves a significant investment and the build out of a large team. If the company is successful in building the technology and the market grows quickly – a successful exit can be secured. However, markets often take a long time to grow and this provides an opportunity for established companies to catch up and reduces the potential value in an exit. This vertical approach requires a large capital investment and the exit potential is somewhat binary – the result is that VC’s and investors have recently been less willing to invest in new semiconductor business.

As a result of the large amount of capital required and the reducing number of large scale IPO and M&A semiconductor exits – funding for semiconductor companies is drying up. The GSA has identified that the lack of new start-ups is leading to a reduced level of innovation and is creating a problem for the industry as a whole.

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