III-V high mobility semiconductors for advanced CMOS apps

Clement Merckling, imec, Belgium, presented on the epitaxial growth and in-situ passivation requirements for III-V high mobility semiconductors for advanced CMOS applications at the Semicon Europa in Dresden, Germany.

The motivations for III-V MOS transistors include higher electron carrier mobility (@ low-field), more efficient source injection, smaller energy bandgap, VDD scaling, band engineering capabilities, lower temperature processing, high-K gate first process possible and 3D compatible architecture.

The International Technology Roadmap for Semiconductors (ITRS) believes in Ge and III-V. IMEC epi + in-situ oxide 'tool park' involves MBE (molecular beam epitaxy) and MOVPE (metalorganic vapour phase epitaxy) III-V growth techniques. The III-V EPI is clustered with in-situ oxide capabilities.

The AIXTRON Crius 300mm looks at III-V selective epitaxial growth (III-As and III-P). The AMAT/RIBER III-V logic cluster 300mm looks at the III-V selective epitaxial growth (III-As and III-P), in-situ surface analysis, handled by RIBER ISA 300, and oxide (ALD and MBE) chambers in-situ.

The RIBER MBE 49 cluster 200mm looks at the III-V solid source epitaxy (III-As and III-Sb) oxide chamber in-situ.

Main issues and challenges
Main issues for III-V integration include III-V integration on Si platform. There are all sorts of crystalline defects. Next, gate stack formation on MOS. It is much more difficult to passivate interfaces. Smaller bandgap, means, an increased Ioff due to band-to-band-tunneling.

Challenges with III-V heteroepitaxy on Si include Lattice mismatch, anti-phase boundaries (APB), mismatch stress relaxation and related defects such as dislocations at interface, and extended defects (threading arms, SFs). There are other defects caused at isolation interfaces, such as twins, stacking faults, facets, etc. Finally, there is interdiffusion at heterogeneous interfaces.

However, it is possible to achieve high quality heteroepitaxy by direct epitaxy using metamorphic buffer and defect confinement and wafers bonding. Strain relaxed buffer (SRB) is among the options for III-V materials integration at imec.

There can be InGaAs metamorphic buffer, with the MBE growth of low defect density and device quality III-V heterostructure using a suitable metamorphic buffer. Or, there can be III-Sb on Si by SS-MBE, that provides a route to relax III-V.

Defect confinement is possible via 'necking effect'. The selective area growth (SAG) of III-V compounds via MOVPE (or CBE ?) means the defects are trapped at trench edges. The other way is dislocation trapping in narrow STI trenches for aspect ratio >2. There is low defect density material in the upper part of the trench.

Elimination of APBs for on-axis Si (001), Si recess engineering, is possible either via rounded-Ge surface or V-grooved surface. In the rounded-Ge surface, step creation is done by surface engineering of a Ge seed layer. Double steps on a Ge surface are more stable and easy to form with a lower thermal budget than on Si.

In V-grooved surface, (111) surface is obtained either by KOH or TMAH wet etching. Growth inside a pre-defined Si {111} enclosure promote initial III-V nucleation uniformity.

The 'necking effect' approach presents its own challenges. One, perpendicular view, where there is efficient defect necking effect with side wall and parallel view, which allows viewing high defect density.
Defect in III-V MOS stack
There is a need to avoid exposing the III-V surface-to-air before growing the gate dielectric. There is a RHEED (reflection high-energy electron diffraction) study of surface reconstruction and gate stack formation. In the first RHEED of 300mm Si surface, clear 2x1 surface reconstruction wsa observed after bake and transfer in cluster.

In conclusion, the integration of III-V high mobility material in CMOS on 300mm Si substrates requires manufacturable solutions. The SEG hetero-epitaxy is powerful, flexible approach. However, the MBE approach also shows high potential, SRB options.

Key issues include epitaxy: defect formation. The intrinsic defects include Lattice mismatch, such as, necking effect; polar/non-polar, like double atomic steps, and extrinsic defects (interaction with side walls).

Gate stack, passivation is another issue. This includes oxidation and surface control, surface reconstruction and UHV in-situ analysis. Important progress has been made so far. Much more work is required.