2009 DRAM CAPEX decreased by 56 percent: DRAMeXchange

The 2008 DRAM chip price dropped more than 85 percent, while the global DRAM industry has faced more than two years of cyclical downturn, and the consumer demand suddenly froze because of the global financial crisis in 2H08.

In 1Q09, the DDR2 667 MHz 1Gb chip price rebounded to an average of US$ 0.88, which fell between the material cost and cash cost level. Still, the DRAM vendors encountered huge cash outflow pressure. Not only were capacity cut conducted, the process migration schedules were also delayed in the wake of respective sharp CAPEX cuts.

According to the survey of DRAMeXchange, the worldwide DRAM CAPEX of 2009 has been revised down to US$ 5.4 billion, sharply down by 56 percent, in contrast to the US$ 12.2 billion in 2008.

WW DRAM 50nm process migration schedules all deferred one to two quarters
From the roadmaps of DRAM vendors, the adoption schedule of DRAM mass production using the 50 nm process have now been delayed one to two quarters. DRAMeXchange estimates that by the end of 2009, the DDR3 will account for 30 percent of the standard DRAM.

Regarding the new DDR2 and DDR3 process migration, all DRAM vendors still own different types of strategies of density and types. For example, the Korean vendors’ 50 nm process migration schedules of DDR 3 are earlier than DDR2 and the 2 Gb DDR3 mass production schedule is earlier than the 1Gb chip.

As for the US and Japanese vendors, according to their DDR3 roadmap, the 50 nm process will be introduced between 3Q09 and 4Q09, which is later than the Korean vendors, and also firstly with mass production of 2 Gb DDR3. Therefore, in the DDR3 era, the density will mainly be 2 Gb which is a lower cost driver with more stimulating incentive to the market demand of higher density chips. The Taiwanese vendors are under the high cash pressure and are falling behind in the 50 nm process race. They are mainly focused on “pilot production”.

Gross die increases 40-50 percent as 50nm process drives down cost
According to the Moore’s Law, the number of transistors on an integrated circuit doubles every 12 months. After the process shrinking became more difficult in the recent decade, it increased to 24 months. With new process migration, the closer the line distance is the larger gross die number a single wafer gets, meanwhile the cost is lower and the vendors gain more competitiveness.

The average DRAM output increased about 30 percent during the process migration from 70nm to 60nm. With improvements of process design and die shrink in the same generation of process technology, the output can once again increase 20 percent. In the 50nm generation, the output will increase almost 40-50 percent, compared to 60nm process and the number of gross die increases to 1500-1700 per 12 inch wafer with another 30 percent cost down.

Cost of immersion lithography tools major capex of 50nm process migration
The major challenge of 50nm process migration is the lithography technology. The newest immersion lithography equipment is required and the older exposure equipment at the wavelength of 193nm is no longer suitable under 65nm process, due to physical limitations.

Traditional dry lithography uses air as the medium to image through masks. However, immersion lithography uses water as the medium. Immersion lithography puts water between the light source and wafer. The wavelength of light shrinks through water so it is able to project more precise and smaller images on the wafer. This is the invention that enabled the semiconductor process technology to migrate from 65nm to 45nm.

The current major immersion equipment vendors are ASML, Nikon, and Canon. The largest vendor in the market is AMSL, which is now mainly promoting its XT1900Gi, a tool that is capable to go lower than 40nm and is the most accepted model in the industry. Nikon still promotes its NSR-S610C, which was launched in 2007 and is able to go down to 45nm process. Canon launched its FPA-7000AS7 in mid 2008 that supports the process under 45nm.