Monday, May 24, 2010

Xilinx’s ISE Design Suite 12.1 focuses on power, productivity and plug-and-play!

Early this month, Xilinx Inc. released the ISE Design Suite 12. I remember, last year, around the end of April, the ISE Design Suite 11 had been released, so this release should surely have some new things to offer, considering that this is among Xilinx’s key milestones this year.

Just for the record, so far, Xilinx’s notable milestones for this year have been: 28nm architechture supported by clock gating, partial reconfiguration in February 2010, followed by the release of the AMBA 4/AXI-4 specifications in March. And now, the ISE Desgin Suite 12.1, which incidentally, is available from May 3, 2010, onward.

For those who came in late, Xilinx’s ISE Design Suite 11.1 (released a year ago) was said to be the industry’s first FPGA design solution with fully interoperable domain-specific design flows and user-specific configurations for logic, digital signal processing (DSP), embedded processing, and system-level design.

What’s new with ISE Design Suite 12.1?
Now, what’s new in Xilinx’s ISE Desgn Suite 12? Three things — power, productivity and plug-and-play!Xilinx’s ISE Design Suite 12′s thrust has been on improving the power efficiency (or power reduction), productivity and plug-and-play capability. Let’s take a look at each one of them.

On power, Xilinx claims to have achieved (or made available) 30 percent dynamic power reduction using the innovative automated clock gating technology. On productivity, the ISE Design Suite 12 boasts of improved productivity with design preservation, faster run-time and fourth generation partial reconfiguration. On plug-and-play, the Design Suite 12 allows plug-and-play FPGA design with AXI-4 compliant IP.

I will try and add some more details on the three aspects, time permitting.

Xilinx has also outlined the next steps in the ISE Design Suite roadmap. These are:

* In May 2010, it has introduced intelligent clock-gating for Virtex-6 and and improved the design preservation

flow for timing predictability in ISE Design Suite 12.1
* In the summer of 2010, Xilinx will offer partial reconfiguration to all users and intelligent clock-gating support for Spartan 6.

* In the fall of 2010, Xilinx drives plug-and-play FPGA design with embedded, DSP and connectivity IP support for AXI4.

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