June '10 global semicon update: Forget 2010, ~30 percent’s in the bag! What about 2011?

Here are the excerpts from the Global Semiconductor Monthly Report, June 2010, provided by Malcolm Penn, chairman, founder and CEO of Future Horizons. There are a lot of charts associated with this report. The report also covers market trends. Those interested to know more may contact Future Horizons.

April set the ball rolling for a blockbuster second quarter making what will now be five successive quarters of growth. Our 3 percent Q2 growth forecast looks increasingly timid, with 6-8 percent more likely. Virtually all forecasters are now pitching 2010’s growth at the 30 percent level, so there is little left to argue about other than guessing the exact final number.

Whether the ‘final’ number is 28 or 38 percent really makes no odds; it is the underlying trend that counts, something we forecast correctly over 18 months ago.

The real issue now is “What about 2011?” We are clearly now in a boom and the next phase is bust, but when, how deep and how fast will it collapse? We are currently reappraising this and our 2011 forecast, with the analyses to be presented at our forthcoming IFS2011 Mid-Term International Forecast Seminar in London on 20th July.

Forget all of the intellectual arguments about expanded geographical customer base, broader application range and the smoothing effects these would have, all that is hogwash. The industry boom-bust cycles persist and will continue to do so all the while demand dynamics are measured in weeks and the supply-side in quarters making it impossible to ever balance supply and demand.

At this point it is pertinent to revive a slide I first presented at the IEEE meeting in Boston in 1975. This slide is as valid today as it was 35 years ago.Source: Future Horizons, UK.

After four quarters of growth, the industry now finds itself in the full flood of a classic market boom. Order books are full, customers are building stocks, double ordering is rife, capacity is strained, lead times increasing and deliveries are stretched.

Inventory replenishment started in Q2-2009, due to the severe inventory overdepletion in Q4-2008/Q1-2009, and was over by Q4-2009 to be replaced by inventory building in 1H-2010, driven by lead-time extension.

Typically every week of extra lead-time adds at least half a week to WIP. Double, even triple, ordering (due to supply shortages) only really started in 1H-2010 and is definitely getting worse, but double ordering is NOT double shipping, yet. For that to happen, supply needs to catch up with demand. That leaves just one item missing from the 1975 list … ‘prices stabilise’, the worldwide semiconductor and IC ASP trends.

Despite four quarters of growth, no spare capacity, long lead times, low inventory levels and double ordering rife, far from stabilising, no only are ASPs LOWER than they were pre-recession but they are still FALLING! Not so with memories, where pricing hit the increase button at the first sign of ‘sold out’ and are already not only BACK to their pre-recession level but also still RISING.

Time perhaps for a quick reminder on supply and demand economics. Price equilibrium occurs at the intersection of the demand and supply curve, at which point customers get the product they want, at a price they can afford and the seller sells all he can make with no spare capacity.

If demand then increases, but capacity cannot keep pace, the selling price rises until a new equilibrium is reached. Likewise if demand falls short of capacity (the normal case for the chip industry) prices will fall, the theory here being that price elasticity increases demand such that equilibrium is once again achieved.

In the real market place equilibrium can only ever be reached in theory, and the prices of goods less elastic, other than perhaps with memories, but one thing is clear. If demand exceeds supply, time to increase selling prices, if not for the economic theory then at least for return on investment.

Time to increase semiconductor prices everywhere. It is absolute business, economic and industry madness to keep decreasing prices in a tight supply market. As for the argument, what about loyalty to key customers? Ask them what their loyalty was like to you over the past several years, constantly playing off one supplier against another. Then sit down for a serious price negotiation selling capacity, not chasing purchase orders, based on a minimum five year rolling contract with cast iron, non-cancellable commitments. That way industry will finally have long-term order commitments, capacity planning can be improved and investment risks shared.

The chip industry always delivers more bang for the buck, selling on a cost plus not value basis (with few exceptions) and passing on 100 percent of all cost reductions to its customers. Its recent reward has been a decade of ‘no growth’ in value term as a result of five years or more ASP decline, doing more for less. It desperately needs to rebuild its cash, profit and investment position if it is to recover and survive both the trawl to even More Moore and More than Moore, let alone the transition to 450mm substrates and EUV lithography.

Time for a change in chip industry business practise; the current adversarial ‘business as normal’ model is as time expired as the Neolithic.

Industry capacity
Overall MOS wafer fab capacity decreased 2.9 percent in Q1-10 versus Q4-09, from 1,884k 200mm equivalent wafer starts per week to 1,830k. Only 300mm leading edge capacity showed any increase in the quarter, at around 1.2 percent growth. This decreased brings the total capacity decline to 14.7 percent since its Q4-08 peak, with Q1-10 capacity down 5.8 percent Q1-09. In contrast IC unit shipments were up59.6 percent over the same time period.

At 595k wafer starts per week, Q1-10 200mm capacity continued its absolute value decline, from 640k in Q4-10, a fall of 47.1 percent. 200mm capacity is now down 18.9 percent versus the same period last year.

The 300mm wafers now account for 58.6 percent of the total MOS capacity, up from 56.3 percent in Q4-09 and 50.1 percent from the same period last year. Advanced capacity (i.e., 0.06 micron and below) grew 6.3 percent or 42.2k 200mm equivalent wafer starts per week, as leading-edge designs migrate to the 5* and below nodes, memory and MCU driven.

As correctly predicted 12 months ago in our June 2009 Report Capacity review, the combination of capacity cutbacks and recovering IC demand caused total MOS IC Q1-10 utilisation rates to reach the ‘sold-out’ level, at 93.2 percent, up from 89.2 percent in Q4-09 and 57.1 percent for Q1-09. Advanced IC capacity, i.e. 0.06 micron and below, reached 97.0 percent (from 96.2 percent in Q4-10), whilst 300mm and 200mm wafers checked in at 96.6 percent (Q4 = 96.7 percent) and 91.2 percent (Q4 = 82.4 percent), respectively.

It doesn’t get more ‘sold out’ than this … and this at the START of the IC recovery cycle. Given the further 46 percent cut back in 2009 Cap Ex spend, itself down 31 percent on 2008’s level, Cap Ex entered 2010 down one third on its 2007 level despite the same unit demand run-rate level. That implies either a 3x productivity improvement by line width shrinkages and other yield improvements or capacity is going to get scarcer than hen’s teeth.

The first is impossible; the latter is reality. Foundry price will rises, lead times will increase, allocations are inevitable, and premiums for priority delivery the new rules of engagement. 2010’s capacity cannot increase much beyond today’s level, with 2011’s increase dependent on 2010’s Cap Ex, which although is currently running 2x 2009’s level in actual terms only takes 2010 back to its 2007 spend level and too late to impact before Q1-11.

This means capacity will be tight through at least mid-2011. Just as with the chip firms/OEM ‘adversarial-based’ business relationship, so too is the equipment and materials/chip firms business model broken.

Again, what is needed here is a guaranteed five-year rolling order book guarantee, little wonder under the current system there is so little stomach to support the 450nmm wafer transition, not helped by the fact there are too few customers to spread the risks over. The industry has only itself to blame for this mess.