According to Yole Developpement, France, the number of devices packaged with 'fan-in WLCSP will exceed 25 billion units in 2012, exceeding more than 2 million 300mm equivalent wafers. Yole recently held a seminar on wafer level chip scale package (WLCSP).Source: Yole Developpement, France.
Yole estimates the fan-in WLCSP industry value to be over $1.9 billion in 2012. This includes wafer level services (including test) and die level services, as well as the service margin. This market value is expected to keep on growing at a 2010-2016 CAGR of 12 percent, despite decreasing prices. However it does not grow equally across all device types.
The use of fan-in WLCSP for a given application tends to be more and more standardized: it is now clear, for example, that the penetration rate of fan-in WLCSP for connectivity devices in handsets is close to 100 percent, while some players still proposed QFN or BGA solutions a couple of years ago for this same application.
The maximum die size increased recently, and it is now common place to find 36mm² fan-in WLCSP devices in smartphones and tablets. The world record is 50mm² with 309 balls. Any fan-in WLCSP device larger than 4mm in side needs to be underfilled on the PCB. According to Yole, fan-in WLCSP is a maturing technology and market. It still grows faster than the average semiconductor packaging market mainly thanks to the fast growth rates of smartphones and tablet PCs in which WLCSP considerably helps save space and costs.
WLCSP has been extending to higher I/O levels in PMU applications. The largest WLCSP IC on the market: Fujitsu MB38C311A, which has 309 WLCSP balls: world record highest WLCSP pin count, measures 50mm² and has 0.4mm pitch. It has been designed and manufactured by Casio Micronics (now TeraMikros) and uses balls on copper posts: eWLP technology. The PMU and audio interface functions have been combined. It is found in the Sharp SH-01A phone.
WLCSP has also been used for an audio amplifier. By using WLCSP, the audio control chip and amplification IC of the iPod Shuffle could be squeezed in the headphones, making it compulsory to use the Apple headphones or some specific headphones under Apple license (the shuffle device has no audio circuitry). The IC (1.35 mm x 0.85) is made by Texas Instruments.
VTI – 3D axis accelerometer provides a 3D-WLCSP example. The WLCSP package of the CMR3000 integrates two dies (ASIC + MEMS). The ASIC die is flip-chipped on the MEMS die (the gap between the 2 dies is underfilled). The ASIC die is manufactured using a CMOS technology with a 0.4μm process. The MEMS die is manufactured using three bonded wafers (c-SOI sensor + Cap) processed with bulk micromachining technologies.
And, when is WLCSP more appropriate with respect to the other WLP technologies? WLCSP is a wafer-level based package technology with no need for a fan-out area. It applies to low I/O density ICs with a limited die size (generally lower than 30mm²) and fine ball pitches to the application PCB (equal to or lower than 0.5mm).
WLCSP market value forecast WLCSP and 3D-WLCSP
The total market value (subcontracted + insourced) of the WLCSP wafer and die assembly services, final test included, based on the price of the subcontracted service by OSATs. The fan-in WLCSP market value totaled close to $1.4 billion in 2010, of which $1,091 million was for WLCSP of ICs and $300 million of CMOS image sensors and MEMS.
The 3D-WLCSP market is likely to grow at a 2010-2016 CAGR of 25 percent fostered by the fast growth rate of MEMS and CIS and by the acceleration of the penetration of WLP packages for these devices. The WLCSP market value for integrated circuits is likely to grow at a 2010-2016 CAGR of 7 percent. It is significantly lower than the 16.5 percent growth rate of this market as expressed in 300mm equivalent wafers over the same period of time due to declining margins and fast adoption of lower cost WLCSP on 300mm wafers (in terms of cost per die).
Drivers for WLCSP include footprint reduction, electrical performance, legacy die converted to WLCSP through use of RDL (lower price and no need for silicon redesign), thin package profile (Z < 1.0mm) and cost is competitive with other package types.