Friday, March 1, 2013

Flip-Chip: An established platform still in mutation!

Flip-Chip is a chip packaging technique in which the active area of the chip is flipped over facing downward, instead of facing up and bonded to the package leads with wires from the outside edges of the chip.

Any surface area of the Flip-Chip can be used for interconnection, which is typically done through metal bumps. These bumps are soldered onto the package and underfilled with epoxy. The Flip-Chip allows for a large number of interconnects with shorter distances than wire, which greatly reduces inductance.

According to Lionel Cadix, market and technology analyst, Yole Developpement, France, metal bumps can be made of solder (tin, tin-lead or lead-free alloys), copper, gold and copper-tin or Au-tin alloys. The package substrates are epoxy-based (organic substrates), ceramic based, copper based (leadframe substrates), and silicon or glass based.
In the period 2010-2018, Flip-Chip will likely grow at a CAGR of 19 percent. In 2012, laptop and desktop PCs were the top end products using Flip Chip. It represents 50 percent of the Flip-Chip market by end product with more than 6.2 million of wafer starts. PCs are followed by smart TV and LCD TVs (for LCD drivers), smartphones and high performance computers.

The Flip-Chip market in 2012 is around $20 billion, selling 20 billion units approximately in 12" equivalent wafers. Taiwan is so far the no. 1 producer. At least 50 percent of the Flip-Chips devices get into end products. By 2018, the Flip-Chip market should grow to a $35 billion market, selling 68 billion units.

Applications and market focus
Looking at the Flip-Chip applications and market focus, Flip-Chip technology is already present in a wide range of application, from high volumes/consumer applications, to low volumes/high end applications. All these applications have their own requirements, specifications and challenges!

Some of these applications are military and aerospace, medical devices, automobiles, HPC, servers, networks, base stations, etc, in low volumes. It is present in set-top boxes, game stations, smart TVs/displays, desktops/laptops and smartphones/tablets in high volumes. Flip-Chip applications are in imaging, logic 2D SoCs, HB-LEDs, RF, power, analog and mixed-signal, stacked memories, and logic 3D-SiP/SoCs.

In computing applications, for instance, the Intel core i5 is the first MCM combining a 77mm2 CPU together with a 115mm2 GPU in a 37.5mm side package. Solder bumps with a pitch of 185μm are used for the slicon to substrate (1st) interconnect. This MCM configuration is suitable for office applications, with relatively low demanding processing powers. For mobile/wireless applications, there are opportunities for MEMS in smartphones/feature phones. Similarly, Flip-Chip is available for consumer applications.

For microbumping in interposers for FPGA there is a focus on Xilinx Virtex 7 HT. Last year, Xilinx announced a single-layer, multi-chip silicon interposer for its 28nm 7 series FPGAs. Key features include two million logic cells for a high level of computational performance, and high bandwidth, four slice processed in 28 nm, 25 x 31mm, 100 μm thick silicon interposer, 45 um pitch microbumps and 10 μm TSV, and 35 x 35 mm BGA with 180 μm pitch C4 bumps.



Even if the infrastructure had been ready for full 3D stacking, the 2.5D Interposer would still have been the right choice for FPGAs since the '10,000 routing connections' would have used up valuable chip area, making the chip slices larger and more costly than they are now. Virtex 7 HT will consist of three FPGA slices and two 28 gbps SerDes chips on an Interposer capable of operating at 2.8 Tb/sec.

Another example for micro-bumping for memory and logic stacking is in ST-Ericsson's WIOMING. WIOMING is based on the WIDE IO JEDEC standard for SDRAM (for mobile applications). The wide IO DRAM is stacked on an application processor (APE). There is face to back stacking with TSV in the APE SoC.

Next, 3D digital to analog stacking has been demonstrated by STMicroelectronics. The 3D system partitioning for wireless applications concept has been successfully demonstrated with TSV, seven metal layers and Cu pillar to Cu pillar die to die connections.

DDR memory could move from wire-bond to flip-chip. Flip-Chip will probably be adopted for HVM of next generation of DDR memories (DDR4) and also for memory stacking in the frame of a 2.5D or 3D integration scheme. Flip-Chip will be mandatory to reduce the parasitics and improve electrical performance of memory cells running at high frequency (typically > 10GHz). The expected benefits while moving from wire-bonding to flip-chip include:
* Reduced crosstalk (both capacitive and inductive).
* Better signal integrity.
* Lower delay.
* Reduced power consumption.
* Smaller package.

Drivers and benefits
Some of the drivers and benefits provided by Flip-Chip include high I/O density, large die-to-package fan-out area and interconnection to fine-pitch substrate, besides electrical performance/interface bandwidth, thermal dissipation, hermeticity, ergonomics and topology.

In 2012, bumping technologies, including solder bumping, C4, copper pillar bumping and gold bumping (plated bumps and stud bumps), accounted for 81 percent of the total installed capacity in the middle-end area.

The 2010-2014 middle-end capacities forecast revealed that the Cu pillar capacity is likely to grow fast on the 2010-2014 time frame (31 percent CAGR) hitting ~10 million wspy in 2014, to support the growing demand for micro-bumping and advanced CMOS IC bumping. The FC solder capacity will grow slowly (7 percent) on the same period (mix of Sn/Pb solder bump capacity that is phasing out and replaced by lead-free solder). The FC gold bumping capacity is not expected to grow anymore.

Flip-Chip in package (FCIP) accounted for 86 percent of the overall $20.3 billion market, with 14 percent going to the COF/COG (for display drivers).

Wafer bumping trends
Solder bumps have moved on to copper pillars. Pillars of copper are typically plated on the chip in wafer form through photo lithography techniques. Solder bumps have fixed aspect ratios lower than one, whereas copper pillars offer aspect ratio flexibility, and therefore can increase I/O bump densities for many applications in addition to other advantages.

In copper pillars, finer pitches are possible down to 20μm. There is reduced risk of shorts between adjacent bumps. There is larger spacing between adjacent bumps for signal routing and easier underfill flow. There is a high bump aspect ratio. Copper pillars are a reliable lead-free bumping option as well. Copper also offers higher electrical conductivity than solder, and has higher current density capability. However, there can be higher elastic modulus (stress during attach process).

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