Thursday, November 1, 2012
Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.
IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&D pilot line will enable full 450mm process capability for advanced nodes by early 2017.
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture. Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.
IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.
IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.
With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.
IMEC’s 450mm timeline includes adding the first 450mm tool in 2013, and strategic tool partnership to accelerate tool development as well as Î±/Î² tool development and testing. The first litho capability would likely be enabled by 2015-16 timeframe. There will be pre-production tool assessment an advanced patterning development. Between 2017-2019, there will be full 450mm process capability, 450mm manufacturability and advanced process development.
Earlier this year, KLA-Tencor announced the installation of the first 450mm-capable Surfscan SP3 systems. Fully automated, these unpatterned wafer inspection systems are designed to meet the demanding defect and surface quality characterization requirements of the 20nm node and beyond, enabling control of the manufacturing process for 450mm polished silicon and epitaxial silicon substrates.
The Surfscan SP3 450 delivers critical capability for manufacturers of 450mm process equipment, such as wet clean tools, CMP pads, slurries and polishers, film deposition tools and annealing systems. IMEC’s mission is to provide technology innovation pipeline, enable early design/technology co-optimization for fabless and fablite partners, and be a strategic development partner for equipment suppliers.
IMEC’s 450mm value proposition includes advanced technology development on state-of-the art 450mm tools. There will be strategic partnering with the equipment suppliers to accelerate 450mm equipment development cycle in industry-relevant technology flow. The expertise center will be focused on process control and defect reduction.
IMEC will leverage the 300mm experience for scanner setup/monitor/control. It will define the initial set of requirements for tool/process control, develop metrology and process control solutions, and identify ‘wafer size’ related process challenges.
Partner value proposition
Suppliers will make strategic partnership to accelerate 450mm equipment development. There will be a stable tool environment for tool baseline monitoring and testing. Metrology and tool control solutions will be developed, besides a stable demo facility.
The tier 1 ICM will shorten the 450mm learning cycle by supporting equipment suppliers. There will be early learning of 450mm process equipment manufacturability. The 450mm process related challenges will be identified and process control solutions developed. The tier 2 ICM will have early access to process development and remote R&D facility. For fabless and fablite, there will be foundry-compatible process environment that enables design/process co-optimization. They can also assess technology capabilities and limitations, and do cost analysis.
IMEC technology roadmaps
IMEC has technology roadmaps prepared for logic scaling from 1/1.1V up to <0.5V, besides 14nm FinFET or fin-shaped field-effect transistors, made of a compound semiconductor called indium gallium arsenide (InGaAs) platform integration. This platform integration will enable the aggressive 14nm FEOL+BEOL platform and later, scaling the platform to accelerate 10nm and beyond R&D.
There are roadmaps for 10nm high-mobility channel FinFETs as well. This involves heterogeneous material integration, epitaxy and crystal defect control, III-V/Ge FinFE design and modeling, S/D and contact, and gate stack and surface passivation.
Posted by Pradeep Chakraborty at 8:41 PM